If the current exceeds the Iout*Rin > (Vin-Vout) drop on the input for a short time, a storage cap is required to compensate for this will work, as long as the energy dissipation for the input resistor to charge up the cap with power on is not too excessive above its Steady Power rating. Ec=1/2CVin^2 is the cap energy required to charge up from 0 V.
This assumes no output load on startup so Vin=Vin' worst case.
For T=RinCin if this time is < 0.1s it won't have much time to heat up.
A more precise optimum value could be done if there were data to show average and peak currents and voltage drops.
To fully understand your problem, we would need relevant PN's, layout, probing photo and scope traces.
The load current may be handled by the output cap for time durations of about 2% of V/I*Cout=T for 2% transient load regulation with rise times shorter than the LDO loop bandwidth and Tr= 0.35/f
The load regulation error is purely a function of the Rce divided by internal loop gain @ Imax using an equivalent R divider when linear but when VIO drops to zero, the loop gain drops to 1 so it just a low Rce value (at low Vce{sat}) in series with the input cap.
So a 1% load regulation means the regulator is approx 1% Zout of the Rload at Imax. If this Rce is still too high for the current spike thena bigger low ESR cap is needed. However this attenuates the LDO feedback error and if datasheet has limits on this for loop stability, this must be observed then an RLC filter may be a solution.
The same is true for transient load spikes except the ESR of the output cap becomes the source.
The datasheet shows an example of Cset=0.1uF and Cout=22uF ceramic giving an output deviation of 20mV @1Vout @ 0.1 to 1A step load or 2% transient error. Response time indicates ~10us which means the loop bandwidth f=0.35/T for T=10us = 35kHz and Req=T/C=10us/22uF = 0.5 Ohm ESR which may part;y due to cap ESR but steady state ESR from Vin'-Vout = 0.35V/3A@50'C ~ 0.12 ohms.
