Issues with a Sallen-Key low pass filter for turning a PWM into a DC voltage

Question

I need to turn a 490Hz PWM into a DC voltage using a Sallen Key low pass filter.

In the picture, you can see my bode plot and there is -60dB attenuation at 490Hz. The passband has 0dB of gain. The load is the 10k resistor. (Don't ask about the weird capacitor values it's what I got.)

The results from the simulator are perfect. For a 50% duty cycle I got an output voltage of 2.5V.

When I went to build this circuit here's the output I actually am getting:

Now I'm fairly certain that my circuit is working somewhat properly, because here is the signal at the positive terminal of the op-amp.It is a DC voltage of about 2.4V with a little ripple.

Here's what I've done so far to fix the problem:

1. Switched out the op amp for another one to see if it was just broken.
2. Checked to make sure that all of my wiring is correct (it is I've checked 100 times.)
3. Verified component values.
4. I've checked the signal at every "node" and compared it with my simulation. The signal at every single node matches up with simulation except for the output pin.

It feels like maybe the DC part of my + input signal is getting rejected and the ripple is the only thing getting through.

Answer 1

The awful truth is S&K LPF has problems with suppressing the HF spectrum of the square edge is f-3dB=0.35/tR is far greater than the 1MHz or so GBW of the Op Amp. So a spike passes thru and then gets integrated and then held by the low impedance DC output.

Negative feedback is unable to deal effectively with a fast square wave input.

Solution?

Don't use feed forward/back for a LPF using fast rising square wave input that exceeds the bandwidth of the Op amp where gain > ~10 to 1000 depending on noise tolerance.

Use a 2 stage passive LPF.

56k : 220 nF then 560k : 22 nF to a Unity gain buffer with matching feedback R if you care about IiR= input bias offset

When you design something , define all your requirements (SPECS!) or acceptance criteria.

You gave an unspecified LPF somewhere around 1 to 10 Hz with a rise time of 0.35/f-3dB for 10 to 90% tR. That's pretty slow.

If you need a <1 ms rise time, then consider an dual slope integrator with S&H and reset or dual S&H. The dual slope makes it independent of frequency and if biased to Vdd/2 with a CMOS OA, you can get full scale 0 to 100% PWM for 0 to Vdd. e.g. Noise, DC Offset, tolerances, Rise time

Answer 2

I think that you can use an active filter topology - however, not the positive Sallen-Key structure as shown in your description of the problem. The reason is as follows:

With rising frequencies, the open-loop gain of the opamp decreases (this alone is NOT already the problem), but the loop gain as well as the feedback effect are also decreasing. This means, that the output impedance of the gain stage increases (less fedback).

At the same time, a rising portion of the input signal arrives DIRECTLY at the output due to the decreasing impedance of the feedback capacitor. As a result, more and more the ouput voltage is determined by this unwanted portion. As a consequence, the attenuation of high frequency signals is very often not better than 25 ...30 dB.

Therefore, it is advisable to use another lowpass topology - for example multi-feedback or some advanced techniques (GIC-stages).

As an alternative solution you can use a buffer amplifier - in series with the capacitor - in the feedback loop of the S&K lowpass. This buffer does not allow any input signal to be coupled directly to the opamps output.