Class AB power amplifier output clipping when input exceeds 1.7V

Question

I have a 3 transistor Class AB power amplifier that I referenced from a working design which has different design parameters and biasing than what I need.

How I intend on using it, it will be used to drive a 16 ohm 2W speaker and the input is an AC signal with maximum 6V peak. Vcc needs to be 10V. I want 2W max output which requires 5.65V on the output, therefore I mainly want unity voltage gain and only current gain.

The issue is that I did some calculations and changed the voltage gain to 1 by adjusting R4/R1, and lowered the Q-point by adjusting R3 & R4 to allow for larger headroom to prevent output clipping when the input increases, but using calculations for finding Class A amp biasing values don't work because of the biasing diodes used for the push-pull output pair. And even by playing with the Q-point I still get clipping above 1.7V, and lowering the Q-point further starts to clip the bottom peak of the output.

In the simulation attached the green waveform is the input, blue is output of driver transistor's collector, red is the output for a 2V input sine wave.

What can I change to allow for the full input voltage to be seen unclipped at the output? Is it possible to set a Q-point that allows for full voltage swing that I need (11.3Vpp)? What calculations do I need or does this circuit only work with small amplitude input signals? Do I need a different circuit entirely?

For context this will be used as the final stage in a guitar amp project. Thanks in advance.

Answer 1

The configuration of Q3 with both collector and emitter resistors (R4 and R1) equal in value, does provide unity gain at this stage.

This also severely restricts the range of potentials you can achieve at the collector of Q3. Since both R4 and R1 pass roughly the same current, the voltage drop across them is always the same, and the lowest collector potential you can expect (without even considering diodes D1 and D2) is when both resistors have the greatest possible voltage across them. That is, half of the supply voltage \$V_{CC}\$. Q3's collector can't ever drop below \$\frac{V_{CC}}{2}\$.

The problem is worsened by biasing diodes D1 and D2, which "consume" 1.4V between them, so in practice Q3's collector is even further constrained, to between \$V_{CC}\$ and \$\frac{V_{CC}-1.4}{2}\$.

I believe your output is severely clipped, because Q3's collector is over-constrained. You may be better served by an emitter follower, with no such limitation, and unity gain:

^{simulate this circuit – Schematic created using CircuitLab}

In this setup Q3's emitter can vary over almost the full power supply range, always being 0.7V lower in potential than its base.

Bias resistors R3 and R2 are an order of magnitude lower than the values you chose, because Q3's emitter resistor of 100Ω is quite a heavy load for Q3, and to bias it somewhere in the middle needs more base current than your original values would provide.

If you use the "simulate" link for the above schematic, you will find that the quiescent collector currents in Q1 and Q2 and very high, over 1A, which causes them to dissipate well over 6W even when there's no input. This is because biasing diodes tend to "over-bias" the transistors into quite heavy conduction. The usual way to mitigate this is to include ballast resistance between their emitters, to give those emitters some room to manoeuvre. The cost is slightly greater crossover distortion, and slightly reduced voltage gain:

^{simulate this circuit}

Answer 2

For 2W peak at the 16 Ohm load the output voltage has to be 2 x 5.65V = 11,3V peak to peak. In an ideal world you will lose in the emitters of the output transistors at least 0.7V meaning that you need to increase your supply voltage to 11.3 + 0.7 + 0.7 = 12.7V. But there is even more! Output transistors will lose gain as the signal approaches peaks and the current in the load increases, so they must be pushed harder from behind (driver transistor circuit biasing capability for the output transistors), and if it can not be possible, the real peak output voltage will be cut by at least another volt or more for each half cycle of the waveform. You need to add (roughly) 2V to the supply voltage, so it will have to be around 14.7V DC.

Now adjusting the gain: the schematic looks too much simple to be usable, but it will have as it is, a definite input impedance. Just add a resistor in series with your input capacitor so it can form a voltage divider, just try with values from 10k to 1Meg and there will be a value that lets you have correct ratio of voltage output vs voltage input.

Answer 3

The problem is that, for the dc biasing, you need a fairly large voltage across R4 and a smaller voltage across R1 in order to avoid both positive and negative clipping. To achieve, this R4 must have a larger value than R1 which of course will give the stage some gain.

So having achieved mid-supply(ish) biasing and fairly low Q3 emitter biasing by making R4 larger in value than R1 you then need to reduce the overall gain back down to unity by adding a large resistor in series with C1 which will form a potential divider with the input resistance of the stage.

So that the added resistor doesn't have to be too large you will need to reduce the values of R3 & R2 and adjust their ratio to get the required fairly low Q3 emitter biasing that's needed.

So basically, to get the required biasing, its a matter of increasing the gain by increasing the ratio of R4 to R1 and then reducing it back down by adding an extra resistor in series with C1.

You will need to play around to balance the base bias against the ratio of R4 to R1 against the size of the added input series resistor.