After uploading my PCB design for manufacture, I got an error message about an input pin (#14) of one of the ICs (U4; a TDA7560 amp) being connected to GND and GNDA:
Result Source net Source pad Destination net Destination pad R [Ω]
Short GND D1 / 2 NET-(C22-PAD1) C22 / 1 0
Short GND D1 / 2 GNDA D4 / 2 0
Short GNDA D4 / 2 NET-(C22-PAD1) C22 / 1 0
But: I have never defined such a connection in the KiCad schema I had drawn:
There is just one connection to one of the outputs of the mixer chip on the left via coupling cap and nothing more.
Nevertheless, after generating the net file, constructing the PCB layout, and making FreeRoute do all the routings, I got a conductor path (Net–(C22–Pad1)) crossing the net tie (!) between GND and GNDA. See the path highlighted in pink, which should only connect the C22 cap with pin #14 of U4:
It collides both with GND, and with GNDA where the net tie connecting GND and GNDA lies. Is this a bug in KiCad's Pcbnew or FreeRoute?
UPDATE: When correcting the PCB layout, I found out that the net tie was in fact connected to the NET-(C22-PAD1) path with a narrow white line. See the screenshot below. Does this mean that the wrong connection was already in the net list? Then it becomes somehow mysterious why the DRC didn't warn me.