The 74LS192 IC's up count (pin 5) needs a logic 0 in order to count up. I'm trying to debounce the switch so that it doesn't give multiple inputs to the IC.
I've tried this circuit that is used for normally open switches, but my circuit uses a normally closed one.
As in the comments the simple cap on the input pin and two resistors may work fairly well to give some bounce reduction. Also in the comments is the fact that the arrangement will not be symmetrical for the rising and falling switching edges. That is not necessarily a problem, but there is a simple way to get both edges about equal (if that were desired). Just add a diode in parallel with R9 (anode towards the switch), then make R9 the same value as R8. With that arrangement the charging of the cap is mainly through R8 (the diode by-passes R9). The discharge of the cap is then through R9. Because some logic families differ on their switching points you could adjust R8 and R9 for best operation. With that said there is still the issue of slow rising and falling edges that might cause problems. That condition could be improved by using a logic gate with hysteresis. Yet another option would be to use an SR latch, (but then those options do start to become more complicated).
simulate this circuit – Schematic created using CircuitLab
