I want to know that most of the semiconductor top side cooled package have more than one power source terminal. I can understand by doing so you can minimze the loop inductance of gate driver loop howerver it latest HU3PAK of ST it has drain, with terminal 1 as gate and terminal 2 as Kelvin connection and then terminal 3,4,5,6,7 are power sources. What benefit has this sort of architecture?
1 Answer
Kelvin connection is explained here: Kelvin Source Terminal on MOSFETs
Multiple terminals in parallel allow reducing the inductance from the die source connection, to the board. Effectively they act in parallel, though not naively (\$L_\textrm{par} = L_\textrm{pin} / N\$) because there is some mutual inductance between them. But it is still a significant reduction. This reduces loop inductance, permitting higher currents and faster switching rates, without incurring increased EMI, or breakdown, due to ringing of the switching loop.
Note that device (D-S or C-E) inductance acts in a loop with the opposing device (e.g. for a half-bridge) and the nearest supply bypass capacitor(s). When a given transistor switches on (hard switching), it discharges its own capacitance relatively uneventfully (no in-circuit transient effect, but Eoss is dissipated as heat), but forces full supply voltage across the opposite device. This cannot happen instantly, due to its capacitance (Coss), and what results is the step transient response of the switching loop: the series elements of device + stray inductance, in series with Coss. If the turn-on speed is faster than the time constant \$\tau = \pi \sqrt{L C}/2\$, significant overshoot will result. (In the worst case, peak voltage can be more than double the supply voltage, due to the effect of nonlinear Coss.)
Conversely when a transistor turns off (inductive load commutation), its Coss is charged by the load current, and the opposite transistor is discharged. The load current, which used to be flowing into one rail, must be transferred to the opposite rail, and thus the same excitation as above can occur.
(There is no switching transient associated specifically with turn-on in ZVS, or turn-off in ZCS. The above scenario applies any time the inverter voltage is transitioning rapidly between rails, hence, commutation.)
what sort of benifit this sort of architecture has?
See this question. \$\endgroup\$