The scenario can be illustrated simply with a few simulation components:
simulate this circuit – Schematic created using CircuitLab
R1 in part reflects the AC losses of the switching loop, but R1+C1 also includes the explicit RC components you've placed nearby. Note that, as they have fairly long bodies and connecting traces, they can't do all that much -- consider the effect of 10nH in series with them here, for example. Wide-body R and C are preferable, with wide connections of short length, and placed right beside M1 and D1 respectively.
What the ferrite bead does, is simply increase L1, at least momentarily during D1 turn-on.
Which doesn't look very promising in this configuration, and indeed this is as you've discovered.
Not so easy to simulate with the tools here, is the effect of ferrite bead saturation; under load current, it will saturate, meaning its inductance is much smaller (whereas it might be ~1µH at zero bias, it might be 100nH, 20nH, even less, at peak current). The result is less an RLC ringdown waveform, and more an overshoot of given flux (volts peak * pulse width) before saturating. Saturation is given by the area of the ferrite core and number of turns (and properties of the ferrite material itself). (Exact values aren't known for chip beads, unfortunately, but could be measured.)
We reduce overshoot and ringing by:
- Reduce switching loop impedance (\$Z_\text{loop} = \sqrt{L_1 / C_1}\$), so that a peak transient current (switch turn-off current: in this case, about 5A), into that impedance, creates a peak voltage \$V_\text{pk} = I_\text{pk} Z_\text{loop}\$ acceptably low for device ratings and other purposes
- Increase turn-off time / reduce dI/dt, so that \$V_\text{pk} = L_1 \frac{dI}{dt} + V_o\$ is acceptably low
The latter has an obvious knock-on impact on switching loss, of course. But switching loss has a minimum component due to L and C in the switching loop, and so we seek to reduce both inductance and capacitance where possible. Which also has the effect of reducing the loop's time constant, making it easier to avoid exciting it by switching harmonics in the first place.
With modern devices, this is less and less possible: GaN FETs for example are available with 30V 60A ratings, and good luck using them anywhere near full ratings in a hard-switched application like this. But even among Si MOSFETs, we have devices capable of more than their packaging allows.
For a 30V 5A (peak) application like this, a loop inductance of 10nH or so is quite reasonable, maybe more like 15 or 20nH in your layout as shown, and you can simply set gate resistance accordingly to control overshoot.
As you have discovered, we tend to avoid intentionally increasing the loop inductance, such as by adding ferrite beads, but there are cases where it can be reasonable. The main purpose of ferrite beads is to introduce a lossy inductance (instead of just L1, we might have some L || R equivalent), which can dampen the capacitance and stray inductance of a switching loop, but it carries this downside, that the peak switching voltage tends to increase. It can be more reasonable in soft-switching or ZVS applications, where the switching edges are asymmetrical, and added inductance (in certain places) is acceptable.
The most likely purpose of the ferrite bead here, would be to reduce diode turn-off (transistor turn-on) hard-switching ringing. Which the R+Cs may not be able to help with (or fully), due to their own ESL, perhaps forcing such a solution. But it seems it was added erroneously here, as both edges are hard switched.
