How to build an ultra-low power time counter?

Question

Inspired by this question I would like to know how low power you could go with a counter + 32 kHz oscillator (possibly made by yourself).

I found a nice oscillator circuit on a BJT reportedly drawing less than 1.2 µA from 3V.

Unfortunately the counter and/or prescaler parts are a little more tricky. I do not believe you can make low power flip-flops from discrete transistors but most normal logic ICs are not very efficient either (standard counter ICs all draw around 80 µA at room temperature).

I do not want a counter that is integrated into a microcontroller (PIC or AVR or ARM).

Answer 1

There are several issues here...

1. The oscillator circuit on a BJT doesn't quite spit out +3.3v logic levels. Fortunately, you want to use a lower voltage to get lower power consumption. +1.8v logic levels would be compatible with that oscillator-- but then you'd need +1.8 and +3.3v power rails (and probably loose all benefits in your voltage conversion inefficiency.

2. Dynamic power consumption (the power used when things switch) is mostly from charging and discharging the parasitic caps on the various signal lines. The way to reduce that is to use shorter, thinner wires. And by shorter & thinner I mean don't use wires and instead use a chip. Building this from a collection of chips and transistors instead of one chip that does everything will drive your power consumption up.

3. You said no microcontroller, but honestly that's the best way to do this. TI has an ultra low power MSP430 that would run at 32.768 KHz at less than 1.5 uW. As you've already seen, this type of performance is really hard to beat. After a microcontroller, my next choice would be a Xilinx Coolrunner-II CPLD-- but I doubt that meets your requirements either.

To summarize, an MCU will give you the lowest total power consumption. Otherwise your best choice is to use standard logic parts and suffer with something in the several hundred micro-watt range. Making something out of discrete transistors isn't going to be better.

Answer 2

Something better than HCMOS: NXP's Advanced Ultra-low Power (AUP) series. I'll presume you have a 32.768 kHz clock and want prescalers/counters to get 1 Hz from it.

The AUP series is not as extended as the HCMOS but the 74AUP2G80 may be all we need. It contains two D-flip-flops with inverted Q outputs, so that we can make a :2 divider. There's no Q output but that doesn't matter.

To divide by 2\$^{15}\$ we'll need 8 devices, that's a supply current of 4 µA maximum (0.5 µA per device). Dynamic power dissipation depends on the supply voltage, and since we want low power we choose the lowest possible: 0.8 V.

Then dynamic power dissipation is given by

C\$_{PD}\$ is power dissipation capacitance and is 1.8 pF at 0.8 V. Then we have

\$ P_D = 1.8 \times 0.8^2 \times 0.032768 \times 1 + (2 \times 0.6) \times 0.8^2 \times 0.016384 = 0.050 \mu W \$

The two times 0.6 pF is the load of the D input of the current FF plus that of the D input of the next stage. The power of the next stage is half this one's, since only the frequencies are halved, the rest is the same. So that's 0.025 µW for the 16.384:2 stage, and so on. The sum for 15 stages is 0.101 µF. (Binary people don't need a calculator for this: N + N/2 + N/4 + N/8 + ... = 2N). Add the static power of 4 µA \$\times\$ 0.8 V and we have a total of 3.3 µW, which is almost 2 orders of magnitude better than the 192 µA with the HCMOS devices (see my other answer).

Answer 3

For the oscillator I'd use an RTC like NXP PCF8563, which provides a buffered 32kHz output and only consumes about 300nA @ 2V.

For the counter/divider I looked at HCMOS. According to NXP's HCMOS family specification quiescent current for a flip-flop is 4uA maximum, but that's @ Vdd=6V, so it should be lower at 3V. If you use 74HC93s (4 FF per device, you'll need 4 of those to get 1Hz) total quiescent current is 64uA maximum, which agrees with the 80uA you mentioned.
The good news is that at this low frequency dynamic power is far less than that.

Minimum supply voltage for HCMOS is 2V, so working at this voltage should also reduce the current. The PCF8563 even operates at Vdd=1V (since you don't need the interface).

Answer 4

Many impressive solutions offered to date. I could offer a 100 nano watt RTC solution but it does not meet the requirement to be CPU free.

Even the major watch makers such as Casio use CPU cores in their ASIC watch chips.

Once dynamic power is negligible with 32KHz, the drain is controlled essentially by transistor leakage and supply voltage, so the best solutions will be Vdd=1V or less.

1. Microchip: nanoWatt XLP in all non-DSP PIC's 800 nA Real-Time Clock and Calendar
2. SiliconGate: SGC22300 RTC - Real Time Clock Nano Power Series

I also have research articles with schematics of 0.3uW clocks only, but not commercial ICs.

If interested; I can supply more info;

If I may be so bold as to inquire; why stipulate restrictions on implementation if the requirement is for lowest power?

Answer 5

Technically, the method to make the most power efficient (and fastest) circuit (anything) would be a Full Custom IC using the tiniest technology you can find. You'd have to design your own IC layout and have a foundry build a wafer for you.

There are universities that have agreements with some foundries, maybe you could research your local schools for information on that. If they are willing to help you then it would be free.

Static Free's Electric is a great free software to start building your own custom ICs.

Answer 6

If you think about simple ICs, you can get decent power consumption on CMOS chips. You may take single inverter in a chip, and a counter. Run it at some 1.8V, and hopefully it will eat very little :-)