I am trying to simulate a circuit in LTSPICE and it simulates without any convergence problems. However when I copy the netlist into pspice and try it simulate it I get strange results. It keeps saying convergence problems in pspice. However in LTSPICE it simulates the circuit correctly. Does anyone have any ideas why this is happening?
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\$\begingroup\$ Common enough problem I imagine but it is circuit dependent so show the circuit \$\endgroup\$– Andy akaCommented Mar 27, 2015 at 15:39
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1\$\begingroup\$ You need to post your schematic to get an answer to this. \$\endgroup\$– The PhotonCommented Mar 27, 2015 at 15:53
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\$\begingroup\$ about 20 years ago I managed a team of EE's designing an analog IC. The single biggest problem keeping on schedule was convergence in SPICE! we were using PSPICE at the time, have heard of the same issue with HSPICE as well. \$\endgroup\$– hwengmgrCommented Mar 27, 2015 at 16:04
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\$\begingroup\$ since the tools use numerical computation techniques, the starting state is incredibly critical to success of the algorithm. SPICE takes the present state, and applies an incremental time and calculates the "next state", and iterates until it settles at all nodes. then increment and do it again. But you have to start somewhere and thats where convergence for initial state comes in. \$\endgroup\$– hwengmgrCommented Mar 27, 2015 at 16:08
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1\$\begingroup\$ we ended up putting some dummy parts in, like meg-ohm resistors, and voltage sources, to force nodes to be at a different starting state, and that helped. but its trial and error, which makes schedules slip! \$\endgroup\$– hwengmgrCommented Mar 27, 2015 at 16:08
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