100 Mhz clock frequency for a 16 Mhz MCU

Question

I would like to ask what will happen if I set, for example, 100 Mhz as a clock frequency for a MCU, which can operate at maximum speed of 16MHz. Why wont it work?

Answer 1

If the chip is sufficiently over-designed, it might work.

These factors will conspire against it, taking physical, analog and digital factors into account:

• Semiconductor device limitations
  • Heating in CMOS gates is proportional to clock switching frequency, so the device may overheat or thermal noise may cause bit flips
  • Transistors may not be able to switch fast enough to pass the higher frequency signal
  • CMOS leakage current may cause bit flips
• Semiconductor circuit limitations
  • Parasitic capacitance and inductance in the IC interconnects may attenuate high frequency or cause ringing and generally undermine signal integrity, leading to internal communication failure
  • Internal phase locked loops used to generate other internal clocks may fail to stabilize, leading to timing chaos
  • Clock distribution circuits may fail to synchronize cross-chip functions
  • As others mentioned, combinational logic that is normally expected to complete in a certain time may not complete, leading to logic errors
  • Where present, analog VLSI devices (on chip capacitors, resistors) may have inadequate frequency response to deal with higher frequency internal signals
• External systems
  • External ICs may depend on the MCU's clock, and might also exceed their limits
  • A PCB not laid out for the higher frequency might lose signal integrity
  • The MCU will probably not have enough decoupling capacitors, so it may destabilize the power supply's oscillator, experience internal "brownouts", or interfere with other ICs by imposing noise on the power supply lines

Answer 2

It won't meet timing for one. All the paths through the circuitry of the chip are designed to run without errors at a certain speed. Everything is timed to work together it's part of designing a chip. If you go above that speed then you'll violate those timings and start to hit errors.

For instance if you had plenty of time for a signal to go high at 16mhz before the next clock, you have a lot less time when your next clock is coming at 100Mhz.

Another thing to think about is heat. Your package is designed with certain thermals in mind. As your increased clock rate pushes it last this power rate you risk damage as well.

That's a broad way of stating it anyway.

Answer 3

Typical high-speed digital circuits consist of clocked registers and unclocked combinational logic. When the register outputs change, the combinational logic calculates the next value of the clocked registers. The combinational logic takes some time to reach its new correct state. So you must allow a certain amount of time to pass between clock edges so that this process can complete correctly. If you overclock a processor, there is some danger that the combinational logic will not have enough time to reach its correct state, and so the old value will be latched in at a register. This will lead to undefined and incorrect behavior for the processor. Calculation results could be wrong. Program flow may jump to some unpredictable and incorrect address. In short, if you overclock to the point that the processor malfunctions, it will probably not be a graceful or recoverable malfunction. The expression "not meet timing" basically means that the combinational logic will not reach its final stable state prior to the next clock edge.