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My project involves interfacing two analog-digital converters to an STM32F411RE microcontroller. The first ADC is an ADS1191, the second is an ADS1158.

Those two ADCs will have to convert signals simultaneously and their samples retreived by the MCU.

I've been used to work with a single ADC. The program is interrupted as the DRDY (data ready) pin goes low, and the samples are retrieved.

The questions are:

Do I need to make sure the two ADCs share the same master clock? If yes, I suppose I should use the internal clock of one of them, and feed it to the external clock pin of the second one. ADS1191 has an internal clock of 2MHz and requires an external clock of 2MHz. ADS1158 has an internal clock of 16MHz and requires an external clock of 0.1 to 16mHz. Is it safe to use ADS1191 internal clock and feed it to ADS1158? Will I have to sacrifice anything by feeding a master clock of lower frequency (2MHz vs 16MHz)?

Regards,

Laurent.

Clarifications

The "continuous read" mode which I'm used to use with a single ADC consists in connecting an interrupt signal to the DRDY (data ready) pin of the ADC. When data are being sampled, the DRDY pin switches high. Then, when the data are ready to be transferred, the pin switches low. The MCU detects the falling edge of DRDY and starts transferring the data byte-per-byte.

What I'm looking for is to have "correlated" samples, i.e. make sure that two respective samples from each ADC retrieved at the same time indeed correspond to the same time "bin", which might not happen if the respective master clocks show a drift. From the valuable answers below, I conclude the following regarding the use of two (or more) ADCs.

Suggested solution Make sure the two ADCs share the same master clock. In my application I'm able to redirect the internal master clock of the first ADC to an output pin. This clock signal would then be fed to as "external clock" on the second ADC. To reduce the frequency (which most of the time is related to the sampling rate), one can resort to a d-type flip-flop (to divide freq. by two). The principle would therefore be the same as in a single ADC application: trigger interrupt on DRDY of one ADC (the one with shortest hold time). When this first transfer has finished, retrieve samples from the other ADC.

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If you wish to have the same number of samples per second, then you will need to peruse the datasheets very closely. What you specifically mean by 'simultaneously' needs clarification. All I can show you here is how to achieve correlated samples at the same rate.

The ADS1158 shows (datasheet figure 128) shows a fixed channel mode at its simplest with the data rate at Fclk/128. This appears to be the sample rate.

The ADS1191 is optimised for sample rates of <=8kS/s. Using the 8kS/s rate would therefore be the best you can achieve, according to the manufacturer.

There is an option for an external clock on both, so lets see what you can do.

The ADS1191 accepts a 2.048MHz clock (see the datasheet for details of pin connections as the modulator is expected to run at 128kHz).

To get the 8kS/s rate from the ADS1158 in the simple mode above, yields a master clock of 1.024Mhz. Note that there are limited options to change the sample rate in this part

This is fortunate: Generate a master 2.048MHz clock for the ADS1191 and divide it by 2 to yield the external clock on the ADS1158.

If you now start each conversion at the same instant, you will get conversions that take the same amount of time, and the sample rate is correlated.

Note that the 2.048MHz clock for the ADS1191 was only implemented to enable faster SPI access - you should not attempt to run the modulator above 128kHz.

[Update in response to comment]

I suggested a master clock because that was one method of achieving the desired result; as you note, there are other methods.

A D type flip flop with #Q to D is indeed a standard way to divide a clock by 2.

HTH

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  • \$\begingroup\$ This is the answer I was looking for. Now may I ask why you advise to "generate a master clock for ADS1191"? Why not use the internal oscillator signal as input for ADS1158? It is actually possible to redirect that internal master clock to an output pin (ADS1191 datasheet table 3). The questions that follows is: How do I divide a clock freq by 2? My take is a d-type flip flop. Correct? \$\endgroup\$ – olol85 Oct 13 '15 at 12:17
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What you need to decide is: Should they convert the same number of bits in the exact same time, or should they sample at the same time. These are very, very different.

(links to datasheets in your question would have helped me be quicker, by the way) For reference; ADS1191/ADS1192 TI Datasheet and ADS1158 Datasheet

Starting at the same time is easy:

Both chips have a dedicated "START" signal (p10 ADS1191 and p6 ADS1158), which you can trigger simultaneously, and they will start sampling at the exact same time. One running at 16MHz might be done first (depending on the set conversion resolution!!), but does that matter? The analogue signal captured is of the exact same time. That's what that pin is for. ((Edit: One note: The ADS1191 datasheet doesn't specify the START polarity in that table, should look it up further on in the datasheet if you intend to use it. It's probably positive like it says in the ADS1158 table, but best to be sure.))

Converting in the same time has ifs:

If you need them to convert in the exact same time, with the same resolution and both datasheets specify the same number of clock cycles for that resolution (count the if's here!) then, yes, they should be clocked from the same source. But in such a case I would seriously consider using an external crystal oscillator of 2MHz for both, because clearly you have some very specific timing demands that an internal oscillator is not going to give you.

What I'm saying is: If you have reason to be worried about the conversion time mismatch in the order of microseconds (which I think you don't have if you use the start pins to synchronise, but those are details you didn't specify), you don't want to use any internal oscillators. At all.

What I think you meant to be worried about:

If you just want to be 100% sure of the correlation between samples from both, go into the datasheets, look at the START-Signal to Actual Sample/Hold time specifications and see if they match you expectation. I'm thinking they probably will.

What do you lost by clocking a high speed device at a lower speed:

If you do clock the higher frequency capable device with a lower frequency, you will indeed be sacrificing either speed or accuracy or both.

Let's say it can do 16 samples in 1ms at 16MHz (I didn't read that part of the datasheet, so this is hypothetical, not an actual number).

Then, if you clock it at 2MHz, it will only be able to do 2 samples in the same 1ms. If you only need one sample per 1ms and you don't need high accuracy through oversampling: No harm done. If you do want high accuracy, you probably want to over-sample and usually that's done at a factor 4, 8 or 16: Ah, shame: Now it's too slow.

The same goes for needing 4 samples per 1ms. It could do that at 16MHz, but now at 2MHz, it cannot. It's that simple.

Specific timing will come from your datasheet and you have not shared your exact requirements, so checking all of that is entirely up to you.

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  • \$\begingroup\$ My worry was indeed related to the drifting effect of the respective clocks. Say, if both ADCs are set to theoretically push new samples every 1ms (while started at the exact same time), one ADC might be slightly slower as to "skip" a sample once in a while. I think this is what Peter Smith refers to as "correlated samples". What you say about start to hold time is interesting though. \$\endgroup\$ – olol85 Oct 13 '15 at 11:33
  • \$\begingroup\$ @olol85 To correlate the analogue sample points you are only looking at the sample moment, not the conversion time, as identified above. The "START" pin signals when the ADCs "get" the value from the input, the clock speed only determines how fast they convert it to something digital. If you clock them with an accurate and jitter free 1kHz on the start pin and you configured them to allow > 1kSPS, you will get jitter free, correlated samples from both. If you want correlation in free-running mode (untrig'ed) you need exact clock maths as Peter suggests in his answer. See page 28 of ADS1191 \$\endgroup\$ – Asmyldof Oct 13 '15 at 11:43

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