Minimum FPGA clock frequency

Question

I currently work with two FPGAs, Microchip/Microsemi ProASIC3E and AMD/Xilinx Zynq-7020.

In their datasheets, the recommended minimum operating frequency is 1.5 MHz for the A3PE ProASIC3E chip. The minimum frequency for the Zynq chip is not mentioned.

While I can understand the limit of maximum speed the FPGA can clock at, as there are timing issues and stray capacitance issues at overclocked speeds, I do not understand the requirement for minimum clock speed for FPGAs.

Would such FPGAs work if they are clocked at, say, a few hundred kilohertz?

Answer 1

In their datasheets, the recommended minimum operating frequency is 1.5MHz for the A3PE ProASIC3E chip.

Actually, it's fIN_CCC that's specified as 1.5 MHz min in the datasheet for ProASIC3E Flash Family FPGAs.

That's the Clock Conditioning Circuit (CCC) input frequency. A ProASIC3E CCC contains a PLL and other clock circuitry. PLLs have a frequency range that they can lock to, which here is 1.5 MHz to 350 MHz.

The standard clocked logic circuits within FPGAs/CPLDs are registers (flip-flops/latches) and block RAM. There's no IC minimum input frequency for registers, just a rise/fall time requirement. Block RAMs typically don't have a minimum either.

Some FPGAs contain 'hard IP' blocks: dedicated circuitry rather than programmable logic. Some of these, such as internal ADCs, have required clock frequency ranges. Others, such as SPI or some CPUs, again have no minimum clock frequency.