I'm currently reading the book which name is "PCI Express System Architecture" and i need some answers;
1.)How PCI Express Interface sends TLPs(transaction layer packets) to device core(suppose that device is GPU)?Does PCI Express Interface raises a hardware interrupt?
2.)How Pci express device core interpret these packets?
3.)How long time needed for the next packet transmission?How the receiver and transmitter agree when to transmit and receive packets?
There are many layers of abstraction for PCIe interrupts. Perhaps you'd like to read about it at a low hardware level such as this xilinx core. Perhaps you'd be more interested in how an OS handles it.
Transmission latency and flow control are going to be application specific. I'd like to point out that electrically PCIe is full duplex and so flow control is entirely up to the application.
I would recommend exploring the contents of a Linux device driver.
Perhaps you can be more specific with your question. People spend their entire lives specializing in the creation of PCIe handlers.
PCIe is a networking protocol between multiple entities that send each other read and write requests into their respective address spaces. When requests are generated is defined by the devices on the bus. The exchange of TLPs is fully symmetric, so the format is the same whether the CPU writes to an expansion card, an expansion card starts a DMA transfer, or two expansion cards talk to each other.
The CPU and memory are connected to the root complex, which is basically a regular PCIe node that presents the system memory as the addressable address space (in modern implementations, with a protection/translation layer similar to the MMU), as well as a few special addresses that cause interrupts to be sent to the CPU when written to; there are also special TLP packets that correspond to the traditional ("legacy") PCI interrupts.
The same mechanism also works for the GPU, except that the GPU will not understand legacy interrupts. You can simply access video memory in parallel to the GPU, but writing to a command register will generate an interrupt inside the GPU, which redirects the instruction flow.
The PCIe device and the GPU are typically integrated on a single chip to optimize accesses to the graphics RAM, but logically these are different functional units.
Flow control is implemented using credits, on the link layer (so below TLPs). On a direct link, each side advertises how much buffer space is left for packets of a certain type, and the next packet can be sent if sufficient space is available (so packets are never split).
