I'm using a single SPI microcontroller to talk to about 10 boards. Of course, only one of them is actively listening at a time, using chip select (for the unfamiliar, when chip select is high, the SPI inputs are high-impedance)
But, the clock/MOSI lines are going to be connected to all of the boards. There is no end-termination. So when talking to one board, the other 9 are high impedance; so, can I expect 9 back-reflections? If my logic voltage is 3.3V, might I end up with 3.3*9 volts at the source? (!?)
If this is the case, should I series terminate each line according to the transmission line impedance (ribbon cable, so ~100 Ohms)?
edit: Rise times of the digital signals are ~7ns. Time spent high or low is ~20ns.
edit2: My reasoning of 9*3.3 was based on this nice simulation a fellow stack-exchanger made: http://helloworld922.blogspot.com/2013/04/online-transmission-line-simulation.html
If you have no series termination and high impedance, you get up to 2*Vin at the source on the back reflection. That was just one wire; I just scaled that up for 9 more reflections. Is my logic flawed?