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I'm using a single SPI microcontroller to talk to about 10 boards. Of course, only one of them is actively listening at a time, using chip select (for the unfamiliar, when chip select is high, the SPI inputs are high-impedance)

But, the clock/MOSI lines are going to be connected to all of the boards. There is no end-termination. So when talking to one board, the other 9 are high impedance; so, can I expect 9 back-reflections? If my logic voltage is 3.3V, might I end up with 3.3*9 volts at the source? (!?)

If this is the case, should I series terminate each line according to the transmission line impedance (ribbon cable, so ~100 Ohms)?

edit: Rise times of the digital signals are ~7ns. Time spent high or low is ~20ns.

edit2: My reasoning of 9*3.3 was based on this nice simulation a fellow stack-exchanger made: http://helloworld922.blogspot.com/2013/04/online-transmission-line-simulation.html

If you have no series termination and high impedance, you get up to 2*Vin at the source on the back reflection. That was just one wire; I just scaled that up for 9 more reflections. Is my logic flawed?

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  • \$\begingroup\$ What frequency are we talking here? At any rate, no you won't end up with 30V at the source! \$\endgroup\$ – Tom Carpenter Jul 21 '15 at 3:01
  • \$\begingroup\$ see my edit: rise times are order of 7ns, cable length is quite long (a few feet) \$\endgroup\$ – Paul L Jul 21 '15 at 3:02
  • \$\begingroup\$ That's the rise time, what's the bit rate? (i.e. if you had the worst case scenario where you were sending 10101010) \$\endgroup\$ – Tom Carpenter Jul 21 '15 at 3:03
  • \$\begingroup\$ I see, the time spent high or low is typically about ~20ns \$\endgroup\$ – Paul L Jul 21 '15 at 3:04
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    \$\begingroup\$ 50MHz is getting close to the point where you want to start worrying about transmission line effects. Generally what will happen in a multi-point system is the power from your driver will get split down each line, then any reflections will come back and recombine but that shouldn't result in 9x amplification. If they are all identical and have the same voltage (e.g. 2x amplitude from reflection), it is the current that is going to go up - the voltages can't just add on top of each other. It's more likely reflections will cancel in weird ways and simply distort the data signal. \$\endgroup\$ – Tom Carpenter Jul 21 '15 at 3:16
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So when talking to one board, the other 9 are high impedance;

This isn't quite right. The input impedance of the receiver doesn't change when it is listening or not listening. So all 10 loads will be high impedance (or capacitive).

If this is the case, should I series terminate each line according to the transmission line impedance (ribbon cable, so ~100 Ohms)?

This won't do any good. 100 ohms in series with a high impedance is still a high impedance. If you are going to terminate these lines at the receiving end, you would need the termination to be in parallel with the load. But be careful before you do that and make sure your driver can actually drive a 100 ohm load.

Series terminations are more often seen at the source, since the driver tends to be low impedance, and, say, 95 ohms in series with the driver might match a 100-ohm line reasonably well.

If you have no series termination and high impedance, you get up to 2*Vin at the source on the back reflection. That was just one wire; I just scaled that up for 9 more reflections. Is my logic flawed?

Yes, your logic is flawed. Because if you split up the signal to lead to 9 (or 10) loads, only a fraction of the energy would travel down each line. If all the lines were the same length, you'd end up with a total reflection of 2*Vin (or probably a little less because some of the signal would have been reflected back at the fanout point, and returned out of phase with the other reflections).

So what should you actually do?

Depending on your design constraints, you could try

  • Connecting the loads in daisy-chain configuration and provide a parallel termination only at the end.

or

  • Use a fan-out buffer to drive the signal to each load separately
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  • \$\begingroup\$ Thanks fot clarifying. I'm actually buffering the mcu output with sn74bct25244, a 25 ohm line driver. I thought to use the series resistors simply to absorb the reflections; you are saying that wouldn't happen? \$\endgroup\$ – Paul L Jul 21 '15 at 5:06
  • \$\begingroup\$ One other note, the device does go to high impedance when cs is high- so sayeth the datasheet (ad9914) see page 31, unless I misinterpret their meaning? Although it days nothing of sclk, so perhaps that input is never high impedance \$\endgroup\$ – Paul L Jul 21 '15 at 5:09
  • \$\begingroup\$ If you want to reduce the reflections with a termination at the load, you need to put the termination in parallel with the load, not in series. Also, note that 10 100-ohm lines in parallel is equivalent to a 10 ohm load for your driver. Even the 74CBT25244 can't drive all those lines adequately. But since your buffer is an octal and you only need 2 high speed lines for SPI, you can drive maybe 3 '25244 inputs with each uC output, and then each '25244 buffer can drive 3 or 4 fanned-out 100-ohm lines. \$\endgroup\$ – The Photon Jul 21 '15 at 5:12
  • \$\begingroup\$ On the behavior changing when listening, the datasheet is probably referring to the MISO line (the one driven by the peripheral device), not MOSI. The peripheral should present a high impedance to MOSI whether it's listening or not. \$\endgroup\$ – The Photon Jul 21 '15 at 5:14
  • \$\begingroup\$ I see. Parallel Termination at the ad9914 device is really inconvenient and I'd rather avoid it. That board is already made, i was just going to ribbon cable from my line driver to the board. I was hoping the series resistors would swallow any reflected wave. If there is one series resistor oer line that should take care if it? Because as you say the added impedance is trivial compared to the device input. Isn't that what series resistors are used for? \$\endgroup\$ – Paul L Jul 21 '15 at 5:18

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