# FIR Filter 16-Bit

I am trying to implement a 32-tap filter on an FPGA, I can have only 16-bits for the coefficients, and 16bits for the input samples, and my output should also be 16 bits. Multiplying a 16bit coefficient with a 16bit input sample would produce a 32bit result, and adding all the 32 taps would result in 37bits at the output. So how is it possible to get 16bit output?

• Have you considered to implement fixed point FIR? – Marko Buršič Dec 12 '15 at 10:42

## 1 Answer

Rescale it. The filter coefficients should be picked so that they all add up to the 16 bit max value. This should make the max value after the multipliers fit in to 32 bits. Then just truncate the 16 LSBs. In other words, use output[31:16] as the output and pick the filter coefficients do this does not overflow.

• Thanks. The coefficients also contain negative values, so in calculating the scaling factor should I consider the absolute values of the coefficients or should I subtract the coefficients which are negative? – zer0c00l Dec 12 '15 at 7:51
• Sum of the absolute value of the filter coefficients. Now, the other way to do this is to scale the filter so that the largest coefficient is 1, calculate the worst case gain, and then rescale it with another multiplier. This has the advantage of getting a bit more precision with the filter coefficients at the expense of another multiplier. – alex.forencich Dec 12 '15 at 8:07
• should I scale the input samples also using the same technique? – zer0c00l Dec 12 '15 at 8:57
• No, all of this assumes full-range input samples. Although I suppose you could scale the input samples instead of the output samples; the overall effect would be the same. – alex.forencich Dec 12 '15 at 9:43
• but the samples are fractional numbers, shouldn't they be converted to integers? – zer0c00l Dec 12 '15 at 18:17