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I have a strange problem and I couldn't find a solution for 1-2 month.

In my system I have a Tiva TM4C123GH6PM MCU and external 24 Bit ADC(MCP3919). My PWM pin generates 8MHz clock for ADC main clock. ADC conversion automatically starts with this clock.

My problem is that with software/hardware reset of MCU, my ADC readings sometimes goes wrong. It is like "fixed garbage value" comes from external ADC to me with SPI communication.

Only power off/on device solves problem!!!

As a result, there is a problem that occurs with software/hardware reset of MCU in run-time and the problem is solved with only power off/on device.

I don't know it is related with power-cycle issues sth. like this or not.

I really need your experiences with this issue.

Regards

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  • \$\begingroup\$ Have you tried monitoring the SPI bus with a logic analyzer to see what happens when you get bad values? \$\endgroup\$ – uint128_t Mar 18 '16 at 15:05
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    \$\begingroup\$ You're using the PWM peripheral to generate a clock? That's your problem. Scope that signal on reset. \$\endgroup\$ – Matt Young Mar 18 '16 at 15:07
  • \$\begingroup\$ Hello. My gain is 1. I am just oversampling. Yes I scoped SPI bus and saw that the pattern is fixed. As I said, resetting MCU creates this problem. But it is weird that the problem does not occur while power off/on device. It is same with resetting MCU.. \$\endgroup\$ – dredg Mar 18 '16 at 15:16
  • \$\begingroup\$ I observed the PWM clock but everything look as expected. \$\endgroup\$ – dredg Mar 18 '16 at 15:18
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    \$\begingroup\$ Are you sure? The PWM output will float briefly during reset, which is very likely to upset the clock input of the ADC and potentially even trigger latchup. Scope the clock signal during the reset phase and post a picture. Try it with a buffer (preferably scmitt trigger) between PWM and clock input. \$\endgroup\$ – pjc50 Mar 18 '16 at 15:34
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The fact a POR fixes it sometimes indicates to me that something is not being properly initialized.

I would suggest controlling the /RESET input of the ADC with the Tiva and giving it plenty of time before releasing it from reset- tens or hundreds of ms.

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  • \$\begingroup\$ Hello. I think I explained my problem wrong. The problem does not occur after resetting ADC. The problem is related with the after resetting of MCU. There is a really big time between ADC Reset and MCLK \$\endgroup\$ – dredg Mar 18 '16 at 15:22
  • \$\begingroup\$ By the way, I am controlling ADC reset with one of GPIO pins in MCU \$\endgroup\$ – dredg Mar 18 '16 at 15:27
  • \$\begingroup\$ I agree with Spehro: specifically, it is possible that a communication was in progress at the MCU reset and it terminated incorrectly, leaving some (unknown) values in the registers. The only way out of that is to assert the ADC reset pin for the required time, assuming you are not using the 2 wire interface because a hard reset can only occur for either an internal POR or an external hard reset (but that pin only has that functionality in SPI mode). \$\endgroup\$ – Peter Smith Mar 18 '16 at 15:31
  • \$\begingroup\$ Also, you should keep the ADC in reset until the clock signal is up and running. \$\endgroup\$ – pjc50 Mar 18 '16 at 15:35
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Datasheet for ADC:

All the analog biases are enabled during a Reset, so that the part is fully operational just after a RESET rising edge, if MCLK is applied when RESET is logic low. If MCLK is not applied, there is a time after a hard reset when the conversion may not accurately correspond to the startup of the input structure.

Probably some time delay between applying MCLK and RESET would help you.

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  • \$\begingroup\$ Hello. There is a huge time delay between MCLK and reset. I read this part but as I said, the problem does not occur power offf/on device. It only occurs when I reset my MCU in run time \$\endgroup\$ – dredg Mar 18 '16 at 15:19

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