Final installment (promise!) in my set of metal detector circuit questions. This time it's the speaker driver (see images below). When I first saw this, I thought - no problem it's a sziklai pair, which the AoE describes as a super-beta darlington like combination with a lower Vbe. I also figured that the 470uF cap was just for smoothing Vcc...I was wrong (again).
Some breadboard analysis and spice (see images below) tells the story. The cap charges up to hold the voltage at the emitter of Q2 at a saturation voltage above the collector. This (it would seem) kills the beta of Q2 and the overall beta of the sziklai pair drops to (by my calculation) around 25.
I measured the Ib flowing to Q1 on the breadboard (and spice concurs) and it's ~40mA. This all points to the same conclusion: the cap is driving the pair into saturation and the beta is reduced.
But what I can't understand is why? Why would the designer do this?
By the way, in case you're confused by the spice images, I upped the freq from the 555 to 400Hz because I found the 4Hz ticking in the original to be less effective. But, I don't think it alters the general idea of the capacitor.
Complete original documentation to be found here.
I thought I'd simulated the original circuit with a frequency of 4Hz and a 8 ohm speaker, but obviously not (or not correctly). Anyway, it seems that the speaker I'm using (4ohm 2W) is simply too heavy a load for the driver, causing the driver to saturate. Other than that the intention of C1/R2 is all of the points Jim mentions in the comments. Thankyou.