I bought a 16bit, 250kSPS AD7689 ADC. The circuit I am designing will amplify voltage (from 300uV up to 300mV) across a current-sense resistor (by 13x) to match 4.096V reference and feed this into an ADC. Measured voltage will either be DC or <1kHz square wave.

Do I need an anti-aliasing filter before ADC even tho I am just interested in "static DC voltage" (I am not interested in transient voltage)? If so, what should the cut-off frequency be (higher than 1kHz because of odd harmonics?)? Also what filter order should I use? 1st order seems enough to me, as 1kHz is way below half of Nyquist frequency.

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    \$\begingroup\$ The ADC has a 1-pole filter built-in. Not sure about its frequency, it might be enough. \$\endgroup\$
    – pipe
    Commented Apr 2, 2017 at 12:58
  • \$\begingroup\$ @pipe aargh missed that. Edited answer to reflect that. \$\endgroup\$ Commented Apr 2, 2017 at 13:05

3 Answers 3


You need to make sure that noise from aliasing is low enough one way or another.

You mention the signal being 1 kHz square wave, but then say you are only interested in "static DC voltage". Those together make no sense. I'll assume you want to measure the top and bottom levels of this square wave.

The first thing to do is decide how fast you can sample. Aliasing problems reduce with higher sample rate. You say the A/D can do 250 kHz sample rate, but you haven't said if the system it is connected to can do that. In any case, that is way more than you need.

Try two poles of ordinary R,C filtering at maybe 10 kHz or so. If you sample at 250 kHz, then the only signals above 125 kHz will cause aliasing. Those will be attenuated by about 12.52 = 156.

Only you can answer how much frequency content there will be above 125 kHz, and whether attenuating that by 156 (44 dB) is good enough. From your description, I'm guessing it is. If you're not sure, throw another pole at 10 kHz or so at it.

In general, you want to do only enough filtering in analog to reduce aliasing noise to acceptable levels. If you want to find some "average" or whatever, do that digitally after sampling. Digital filters don't suffer from inaccuracies due to part variations, temperature, or non-linear behavior of parts.

For the digital filter, you have to decide what settling time you want. Filter the sample stream so that a step still settles to within your maximum allowed time to within your maximum allowed error.


Yes, you always need an anti-aliasing filter

I am just interested in "static DC voltage"

Which explicitly says "hey, I want a low pass" (to only let through very low frequencies, ie. "the average voltage).

The cutoff frequency depends on what frequency you operate the ADC on – just because it can do 250kS/s doesn't mean it has to run at 250 kHz. You'll have to control the sampling instants by driving the CNV pin yourself, e.g. with your MCU.

But yeah, since it seems that you're only after very low frequencies, go for a very low cutoff frequency – the lower that cutoff frequency, the less noise energy in your signal.

Thus, design of that filter will not really be defined by the cutoff frequency alone, but also by the stop-band attenuation (which might be important to you, but I don't know anything about your signal source, other than it being in a range where simple pieces of conductor can act as antenna and introduce voltages with a comparable magnitude of voltage). And, of course, by technical feasibility – a 10F / 100MΩ RC low pass is a terribly hard thing to build :)

EDIT: As Pipe pointed out, the ADC comes with a built-in single pole selectable switched cap LPF. Might totally suffice – even more so as table 11 from the datasheet says you can configure it to ¼ of the bandwidth. Note, however, that the "less bandwidth means less noise power" still applies; it really depends on what signal your looking at whether this is sufficient or not!

EDIT: as a software-defined radio guy¹, I can only say: go and upvote Olin's answer. He's saying the right thing: A digital filter is easier to implement and far less problematic than an analog one.

Of course, you should still make sure you don't have aliasing in your digital signal – there's nothing a digital filter can do about that once it happened. However, that just means you need strong stopband suppression above \$\frac{f_{sample}}2\$, not a cutoff far below that. It's just mathematical fact that filters can't have infinitely sharp transition from pass- to stopband, so you'd naturally choose one that has a cutoff frequency solidly below the nyquist limit. But that again stresses the fact that cutoff frequency isn't the most critical design parameter here – it's suppression for frequencies above the nyquist limit that might be present in your signal, and that is usually also a function of how "ideal" you can assume your components to be.

For example: If you'd be building a very low cutoff RC filter, you might be tempted to use very large capacitors – but these often have high ESR.

¹SDR's motto is: sample now, ask questions later

  • \$\begingroup\$ “you always need an anti-aliasing filter” but why? I’ve never understood this. As long as he makes sure that he’s not sampling exactly during the rising or falling edge of his square wave (e.g. by taking the min or max of multiple samples) it shouldn’t matter, should it? \$\endgroup\$
    – Michael
    Commented Apr 4, 2017 at 11:26
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    \$\begingroup\$ and that's exactly the point. If you have a way to make sure you don't do that, you're not exactly using an ADC (because your signal is no longer time-continuous, i.e. analog). In general, you can't make sure, and then you need a filter. Also,don't be fooled:the edge is not over when you think it is–the whole system will inherently have some frequency-dependent behaviour and that'll change the edges' shape – Gibb's phenomenon,"ringing" at the edge boundaries,and that'll distort your measurement too.Also, noise!Noise is at every frequency,and the less frequencies hit the ADC,the less of noise. \$\endgroup\$ Commented Apr 4, 2017 at 11:49
  • \$\begingroup\$ @Michael But: this was really short and superficial. You might want to post a question of its own about this! \$\endgroup\$ Commented Apr 4, 2017 at 11:50

Measuring a step change to 16 bits requires 16*6/9 = 11 time constants of settling. More detailed, this is $$bits * (6db/bit) / (9dB/neper)$$ Once the settling has occurred, the ADC can grab a sample; lets allocate 10uS for that.

What is our budget? 1KHz/2 = 500uS/step; 500uS - 10uS = 490uS for settling by 11 Tau; our longest Tau allowed is 40+uS; or 25,000 radian/second; divide by 2pi and the F3dB is ~~4KHz.

With a 4KHz Low Pass Filter, you have high frequency rolloff and accurate measuring of the 1KHz squarewave---but you have to time the ADC start-convert edge to 10uS before 1Khz edge.

Here is model of your system: 300mvpp, amplified by generic opamp 13X, into 16-bit ADC. I inserted 10mV of 60Hz and 120Hz into the Gargoyles Power Supply Interferer, and surprise the power-supply trash limits your measurement to 15.2 bits. But your thermal-noise is also high. However, Vquant sets the floor.

I used the Generic ADC Worksheet to evaluate the settling requirements. enter image description here


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