Print std_logic_vector in hexadecimal (VHDL)

Question

I have an 8-bit std_logic_vector and I would like to print its value (during simulation) as a 2-digit hexadecimal value.

Current code:

report "Entity: data_in=" & integer'image(to_integer(unsigned(data_in)));

Current output:

Entity: data_in=16

Desired output:

Entity: data_in=10h

What would be the most painless way to achieve this?

Answer 1

In VHDL-2008, one can use:

report "Entity: data_in=" & to_hstring(data_in) & "h";