2
\$\begingroup\$

MCUs have maximum source/sink capabilities per GPIO, maximum source/sink currents through the VDD/VSS pins, and have maximum total power dissipation in function of package.

These parameters are all explicitly declared in the datasheet. For instance, the high current ports on the PIC16 family can output 100mA per pin, the sum of all currents going through the VDD/VSS pins must be less than 250mA, and the package can dissipate 800mW. PIC16F1773 Source/Sink Absolute Maximum Ratings

Does this mean that at any given time the GPIOs can never output more than 100mA on the high current pins, or that this limit can be surpassed (i.e. having a short high current pulse) as long as the total package power dissipation is less than 800mW?

EXAMPLE

Let me give an example to better illustrate my question.

Suppose I have this circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

The datasheet for the IRF8736 states that the input capacitance (Ciss) is 2315pF @ Vds=15V (i.e. non-zero) and a gate resistance of 2.2Ohms, so the instant the GPIO signal goes high, the instantaneous current will be:

\$i = V / R\$

\$i = (Vdriver - Vgate) / Rgate\$

\$i = (5V - 0V) / 2.2Ohms\$

\$i = 2.27A\$

This is way larger than the 100mA maximum allowable current for the GPIO pin.

However, if we look at the power consumed by the driver to drive this signal:

\$Pdriver = Vgate * Qg * Fsw\$

\$Pdriver = 5V * 26nC * 250kHz\$

\$Pdriver = 32.5mW\$

Which is far below the total 800mW allowable by the MCU.

So in this particular case, which parameter should be followed to respect the limits of the MCU? The maximum allowable GPIO pin current, or the total allowable package dissipated power? I wish there was a total allowable power dissipation per GPIO.

\$\endgroup\$
3
\$\begingroup\$

I contacted a few silicon vendors about this question, and I got a variety of responses. The most enlightening answers read as follows (redacted/paraphrased for brevity):

[Vendor A]

The current limit called out in the datasheet is not the absolute maximum current allowed per pin but rather the maximum current for which the output voltage is guaranteed to meet the Voh/Vol specs. For higher currents the output voltage will be outside these limits but the output buffers will function properly.

[Vendor B]

The output buffers have their own output impedance which will limit the amount of current leaving the pin, even when directly shorted to VCC or GND. Therefore no adverse behaviors would occur from directly wiring a pin to a MOSFET gate as long as the power dissipation limits are met.

[Vendor C]

While it is good practice to add a series resistor between the pin and the MOSFET gate, it is not required to protect the output driver. Omitting the series resistor could however introduce a large current delta through GND, which could cause GND bounce.

[Vendor D]

The datasheet is specified for continuous currents rather than short instantaneous pulses, and so it is possible to exceed these limits without causing physical harm to the IC. However, providing guidelines for this operating condition is difficult and would need to be handled on a case-by-case basis.

In other words, it is most certainly possible to have GPIO pins source/sink higher currents for short pulses without damaging the drivers as long as the pin+package power dissipation limits are met. There's no free lunch, however, so proceed with caution.

\$\endgroup\$
  • 2
    \$\begingroup\$ ST actually states in the datasheet that normal GPIOs can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed VOL/VOH). And that the Voh/Vol change on the entire port if more pins are active. Thus one high current pin might still have an effect on the entire port. Beware of that. \$\endgroup\$ – Jeroen3 Nov 7 '18 at 9:02
0
\$\begingroup\$

It means that any single high-current GPIO can sink up to 100 mA. Plus you are bound by 250 mA limit for the whole chip.

You could for example sink 2 x 100 mA using two pins (and be left with 50 mA spare to operate the rest of the chip). You could not sink 3 x 100 mA because you hit the 250 mA limit.

Output current of a pin is shown in FIGURE 37-53 of the datasheet and is much lower than 100mA.

\$\endgroup\$
  • \$\begingroup\$ You are correct, but in reality we regularly break this rule. For instance, turning on a MOSFET using a GPIO. When the MOSFET gate is discharged and the GPIO signal goes high, the is a small period of time where the instantaneous current will be very large, far higher than the maximum allowable GPIO pin current. At which point is the instantaneous current small enough to not damage the GPIO driver? \$\endgroup\$ – TRISAbits Jul 21 '18 at 17:05
  • \$\begingroup\$ It is good practice to place a small resistor between GPIO and MOSFET gate :) electronics.stackexchange.com/a/68754/81178 \$\endgroup\$ – filo Jul 21 '18 at 17:29
  • \$\begingroup\$ It's true, but so many designs don't include the series resistor for small signal FETs. \$\endgroup\$ – TRISAbits Jul 21 '18 at 19:10
  • \$\begingroup\$ You could make the argument that the small signal FETs inside a die don't have a series resistance either, so there's clearly a point at which the small instantaneous current is not dangerous to the FETs. At which point is the high current pulse high enough to warrant a series resistor? \$\endgroup\$ – TRISAbits Jul 21 '18 at 19:23
  • \$\begingroup\$ How does inductance of traces/pins etc effect this? \$\endgroup\$ – Szidor Jul 22 '18 at 6:48

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.