How can the Vss or Vdd pins of a MCU handle sink or source current?

Question

Today I was seeing the datasheet of STM32F103 MCUs and I came across with an interesting thing. assume I have an STM32F103RET6. it's a 64pin MCU of STM32 series. the pinout is this:

It has 4 Vss and or Vdd and 51 GPIO pins (the rest of pins are ain't important for my question). look at Absolute maximum ratings

The total current that all Vss or Vdd can source or sink is 4*150=600mA. as I said we have 51 GPIO pins. if we would use them as source or sink for current then they would draw 51*(+-25)= (+-1275). the point is that the total current that all Vss or Vdd can handle is less than 600mA while the total current for GPIOs is 1275mA. Why?

also that's not only belong to STM32 family. I have checked out AVR family. for example ATmega8a. DIP package:

It has one Vcc and one GND while there are 22 GPIOs. each Vcc or GND (ATmega8a for DIP package just has one Vcc and GND) just can handle 300mA while there are 22 GPIO and the total current is 22*40=880mA. also for MLF or TQFP packages, it's better than DIP because they have a couple GND and Vcc.

Answer 1

All this is saying it that the maximum current, either sinking or sourcing, is 150 mA for the entire chip.. This is probably dictated by heat considerations.

If you had all 51 GPIO pins drawing current, the average would have to be just under 3 mA (150/51) to avoid going over the 150 mA limit. (Actually you could nearly 6 mA per pin, if half were sourcing current and the other half were sinking. But that would be pretty unusual.)

But rather than limit each pin to 3 mA (or 6mA), the spec allows each pin to draw up to 25 mA. But if you have six pins sinking 25 mA each, then you have used up your total of 150 mA and all other pins must not be sinking any current (although they could be sourcing some).