For the CDCE62005 clock generator IC, what does the internal or external loop filter accomplish? Thanks in advance for any input.

Page 44 of datasheet, and pages 1-2 and 6 or the eval board user guide.

CDCE62005 Datasheet: http://www.ti.com/lit/ds/symlink/cdce62005.pdf

CDCE62005 Evaluation Board User Guide: http://www.ti.com/lit/ug/scau024/scau024.pdf

  • \$\begingroup\$ Can point us to what page you're talking about on the spec sheet? I honestly don't feel like going through more than 100 pages of reading to see what you're talking about :) \$\endgroup\$
    – user103380
    Feb 3, 2019 at 17:53
  • \$\begingroup\$ Page 44 of datasheet, and pages 1-2 and 6 or the eval board user guide. Also can control F "loop filter". \$\endgroup\$
    – user127250
    Feb 3, 2019 at 18:16
  • \$\begingroup\$ Edit that into your question if you want readers to see it. \$\endgroup\$
    – Transistor
    Feb 3, 2019 at 18:20

2 Answers 2


Page 44 of 85 shows a 3 caps thus 3 different 1st order LPF’s filter chosen at different breakpoints . So that it starts as a 1st order LPF with R2C2 and then Xc2 drops below R2 at some frequency just below mixer f . This is essential for phase margin and jitter in the defined BW of 2x LPF BW, as 2nd order systems must never become 3rd order if loop gain >1 and the mixer converting frequency to phase error is already an integrator=k/s .

The other cap C1 is 1/10th to 1/5th smaller typically to roll off when the loop gain <1. R3C3 is usually well past 1/f of mixer to reduce jitter further but not induce much phase margin due to phase shift at unity gain.

So it starts as a 1st order filter then flattens out near 0 order then the next LPF’s take effect when the gain is near or past unity gain. The loop gain is affected by the choices of f, the product of MHz/V on the VCO and N divide ratio for multiplying the mixer f to VCO output and phase detector gain in V/cycle

These choices tradeoff jitter, capture to lock time, clock SNR and noise BW

  • \$\begingroup\$ Thanks for the reply. So if I want a 1 GHz clock from the VCO, what would be a proper configuration for the loop filter? \$\endgroup\$
    – user127250
    Feb 3, 2019 at 18:25
  • \$\begingroup\$ Let’s see you do some Bode Plots 1st for amplitude and phase or define every tradeoff I mentioned as a spec. \$\endgroup\$ Feb 3, 2019 at 18:28
  • \$\begingroup\$ I'm learning/refreshing some of the material related to these questions as I go, so it will probably take me awhile. But I appreciate your input so far. \$\endgroup\$
    – user127250
    Feb 3, 2019 at 18:34
  • \$\begingroup\$ You can get formulae but best to define your jitter and lock time 1st \$\endgroup\$ Feb 3, 2019 at 18:52

Loop filters can be 3rd or 4rth order, producing 270 or 360 phase-shifts, but the loop gain must be LARGE in the regions of high phase shifts, to prevent oscillation.

G_large at phase_shift_large


1 + G_large at phase_shift_large * H

may be quite stable, because the G_large is in charge and lets the "H" set the behavior.

When the "G" is low, then the "1" plays a prominent part in the behavior of the closed loop stability.

Its no accident that Harry Nyquist used "1" in his stability criterion.


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