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I'm trying to calculate what I will have to set my microcontroller's ADC sampling rate at in order to sample a band of 500kHz to 1.6065MHz without aliasing. Some constraints here are that I have to work with only 3 high gain-bandwidth product op-amps (conceivably at my level of expertise this means designing a maximum 6th order filter or 3 2nd order stages cascaded) and the maximum sampling rate the ADC can do is 7MSPS in a triple interleaved mode.

I read in a reference book that for a 10 bit ADC the average attenuation at the end of the transition band and beginning of the stop band should be about 62dB down. From the equation for a butterworth filter I work out the sampling rate as follows:

\$A_{min} = 62dB = 20log_{10}(1+(\frac{f'max}{fc})^6)^\frac{1}{2}\$ where \$f'max\$ is the frequency the stopband begins at and \$f_c\$ is the cutoff frequency \$1.6065MHz\$. The power 6 comes from the filter order.

\$(10^{\frac{62}{20}})^2-1\ = (\frac{f'max}{fc})^6\$

\$f'_{max} = 17346kHz (17.3MHz) \$

and according to my reference source \$F_s=2f'max\$ meaning Fs needs to be like \$34MHz\$

This seems really high. Is there a flaw in my math or my reasoning here? It seems that the higher the filter order the lower the sampling frequency needs to be but due to the 3 opamp constraint I can't implement something upwards of a 10th order (for a 10th order filter I work out Fs = 13MHz) and the ADC does a max of 7MSPS.

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  • \$\begingroup\$ What phase response is required ? \$\endgroup\$
    – D.A.S.
    Commented Apr 26, 2019 at 3:27
  • \$\begingroup\$ @SunnyskyguyEE75 I don't think phase response is much of a concern. The project aim is to sample a simple sinusoid amplitude modulated to within the band mentioned above. Then to display the FFT of it on an LCD screen, demodulate in software and output the result via DAC. \$\endgroup\$
    – Blargian
    Commented Apr 26, 2019 at 3:28
  • \$\begingroup\$ Yes you are right, you need a 10th order filter to pass 1.6MHz at -3dB and stop -60 dB at 3.5MHz for a fs=7MHz \$\endgroup\$
    – D.A.S.
    Commented Apr 26, 2019 at 3:39
  • \$\begingroup\$ But you wont have enough GBW to do that (2.5GHz) \$\endgroup\$
    – D.A.S.
    Commented Apr 26, 2019 at 3:43
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    \$\begingroup\$ @Blargian - a)A Butterworth filter may not be your best choice here; an elliptical filter can provide a much much sharper cutoff. b)You should only care about aliasing that folds on top of your signal (0.5~1.6MHz), so if f'max is the frequency where you get the attenuation you want, you only need Fs>1.6MHz + f'max., as opposed to Fs>2*f'max. \$\endgroup\$
    – joribama
    Commented Apr 26, 2019 at 6:56

1 Answer 1

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Lets think about that

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ basically my goal should be to design a filter that attenuates -60dB over the 3.4MHz between the cutoff frequency at 1.6MHz and the start of the aliasing band at 5.4MHz? Or alternatively to oversample such that that aliasing band foldback misses the band of interest? \$\endgroup\$
    – Blargian
    Commented Apr 26, 2019 at 8:12
  • \$\begingroup\$ Yes. But you need to be cautious about the opamp distortion, which will cause beatnotes within the opamps, and will scatter trash all over the spectrum. And the desired region --- 0.5 to 1.6MHz ----- needs to be substantially higher amplitude, so the trash-regions don't overload the ADC's input range. I'd start out the chain of low-pass-filtering with at least one PASSIVE RC LPF, and maybe 2 such filters. Much harder to overload a passive RC LPF. \$\endgroup\$
    – analogsystemsrf
    Commented Apr 26, 2019 at 14:26
  • \$\begingroup\$ thank you for your help. Ended up designing a 6th order passive RLC ladder network and it's working well so far, in simulation at least. Could you explain to me why at these high frequencies active filters don't perform as well as passive ones? \$\endgroup\$
    – Blargian
    Commented Apr 27, 2019 at 14:59
  • \$\begingroup\$ Examine the bottom part of diagram, where I show problems at high frequencies with opamps and PCB parasitics: Rout of Opamp, phase-margin of Opamp, Finite UGBW of Opamp, non-zero Cin of the opamp and of the Virtual Ground node (for the one-pole example I used) \$\endgroup\$
    – analogsystemsrf
    Commented Apr 28, 2019 at 1:25
  • \$\begingroup\$ For anyone interested, the resource below proved to be invaluable in designing a passive RL ladder filter: P. Allen,ECE 6414 - Continuous Time Filters. Integrated Computational Electronics Laboratory Georgia Technical University, 1 ed., 2008. \$\endgroup\$
    – Blargian
    Commented May 29, 2019 at 13:56

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