I am designing an FPGA development board for myself. I want a moderately high speed link (400-500MB/s) to the host PC and I'm considering several options, including an FTDI FT-60x bridge IC. The problem is that this chip has no side channel that would allow me to configure the FPGA, unlike the good old FT-2232H.

This article claims that "USB 2.0 is available on the same connector and can be used as sideband", and suggests using both chips in tandem, with a hub on the USB2 lines for both of them to be available, but routing the USB3 pairs straight to the FT-60x. They are apparently doing this on some of the boards they sell.

So here are my questions:

  • Does the USB specification guarantee that USB2 is still available while using the USB3 lane of the same connector?
  • Can I really skip the hub on the USB3 lane if I'm using one on the USB2 lane?
  • I don't really care if functionality is reduced on a USB2-only port. Can I just skip the hubs altogether and connect one device to each lane?

Ranting, comment, do something else recommendation

meh. FTDI's "our FT-60x can't do an obvious thing, so buy two of our products" isn't sitting all too well with me. Frankly, there's devices that do exactly what you want:

  • First load a USB controller firmware via USB,
  • then download a bitstream to the FPGA via USB3,
  • then communicate with the now functional FPGA at USB3 speeds.

The device I have in mind is the Ettus USRP B200/B210/B200mini… series. They use a cypress FX3.

You can find

  • the schematics of these devices here;
  • the FX3 USB controller firmware here;
  • the host-side userland software (this all works over libUSB, so no custom kernel-mode drivers) here, and
  • the FPGA image source code here.

answering your question

according to https://electronics.stackexchange.com/a/266990/64158 (and the author of the linked answer is really knowledgeable about USB3), yes, you can use a USB3 link without USB2 lines.

However, your host controller and OS need to be willing to consider the two buses separate, if you don't want to use a USB3 hub. In my experiences, that is unlikely to happen if your host is a PC or something similar

If you're, however, in full control of your USB stack (because, for example, you have an OHCI / xHCI in an FPGA at the other end of the link, acting as host), this might work.

  • \$\begingroup\$ Thanks! I knew about the FX3 and I am considering it as well, maybe I should have mentioned this in my question. A minor annoyance is that it requires yet another voltage rail (the FPGA I'm targeting, Lattice ECP5, takes 1.1V for core, while FX3 wants 1.2V), but I guess this is offset by removing a lot of support circuitry and condensing three chips into one. As for the second part of your answer, I already knew that the USB 2.0 lines weren't needed for 3.0 operation, my question was more specifically "can I use both for different things". The host is indeed a PC. \$\endgroup\$ Jun 21 '19 at 6:38
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    \$\begingroup\$ yeah, so if the host is a PC and you can't really twiddle a lot with the internals of its USB controller – no, you can't rely on that working. It might, but I simply wouldn't bet on it. Is an additional 1.2V line really problematic? I mean, it's literally but one or two SOT-something LDOs + two caps more. This would be a design where you'd try to put the LDOs close to the individual power consumers, anyway. \$\endgroup\$ Jun 21 '19 at 7:00
  • \$\begingroup\$ Yes, all things considered it makes a lot more sense to use the FX3 than any combination of FTDI devices. It's a lot more flexible wrt control of the USB protocol, you get a hard CPU "for free", and it also supports USB OTG. The next best thing is using a standalone PHY or high speed serdes modules with a proper USB core on the FPGA, but that's a lot more involved. Marking your answer as accepted. \$\endgroup\$ Jun 21 '19 at 12:11
  • \$\begingroup\$ @Streetwalrus thank you for the kind words. By the way, you could also consider having permanent storage on the device from which you configure the FPGA, so that you wouldn't need the extra FTDI chip; you could then just send some commands to the FPGA to overwrite that memory and reset. \$\endgroup\$ Jun 21 '19 at 13:07
  • \$\begingroup\$ Yeah, that's not uncommon either and I do want to include SPI flash for bitstream storage and application use. Problem is, it's fairly easy to "brick" such a setup. I can always keep a separate JTAG header to fix it but that's a hassle. My current dev setup is a pretty basic Spartan 6 breakout, an FT2232H breakout, and a platform cable clone - 3 USB cables total. I wanted to reduce the clutter and avoid having to touch the board itself while testing. \$\endgroup\$ Jun 21 '19 at 15:07

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