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I understand that some current does flow from drain to source when Vgs is below vth and Vds is greater than zero. Why does this have a different name and a different region in Cadence Virtuoso tool when cutoff and subthreshold both have same behavior? Please explain what am I getting wrong here.

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  • \$\begingroup\$ Is the wiki not clear enough? en.m.wikipedia.org/wiki/MOSFET#Modes_of_operation \$\endgroup\$ Commented Jul 7, 2019 at 13:38
  • \$\begingroup\$ Actually Sir, I want to know If there is any specific boundary(in term of voltages) for the device to enter in subthreshold from cutoff or the current will flow for any small vds? If later is true then whats the meaning of a cutoff region? \$\endgroup\$ Commented Jul 7, 2019 at 14:14
  • \$\begingroup\$ I think it is the threshold where the higher sub-T static currents ( from low Vt channels)meet dynamic current that rises with clock rate. \$\endgroup\$ Commented Jul 7, 2019 at 14:24
  • \$\begingroup\$ In cutoff region \$V_{GS} <V_{TH}\$ and ideally there should be no conduction. But a leakage current indeed flows even in cutoff region. Since this current is flowing when the gate potential is below the threshold voltage this is called sub-threshold conduction. So there is no boundary between the regions. \$\endgroup\$
    – sarthak
    Commented Jul 7, 2019 at 14:28
  • \$\begingroup\$ Technically there can be defined a boundary where dynamic currents meet static leakage \$\endgroup\$ Commented Jul 7, 2019 at 14:29

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MOSFET does not turn off abruptly or the current does not really drop to 0A when the MOSFET is in the cutoff region, which can be problematic.

When Vds is roughly >100mV, Vgs is about or smaller than Vth, and there is some current flow from D to S. This is called the "subthreshold condition"

You will only see this when you are plotting Id vs Vgs since the current is exponentially dependent on Vgs. This also means you will not be able to tell when you are looking at Id vs Vds curve.

This is explained in "Design of Analog CMOS" by Razavi in Chapter 2 section 3.

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