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If I am using a CMOS switch, how much do I have to slow down the switch time so that I don't experience a pop in my audio signal out of my amplifier and how would I accomplish that?

The switch time is currently on the order of nanoseconds which is unnecessary and causing a loud click/pop. The switch basically alternates between two input signals as fast as possible. Currently I'm using the ADG1419, but I can be open to using other chips. I do not want to experience any latency, which I believe is a 3-5ms audible threshold. Thanks!

Update: Here is a picture of my oscilloscope capturing the switch when both audio inputs are the same. I read that in pedal design, if the switches switch to quickly there will be a pop/click. enter image description here

Update: Here is Input (CH2) vs output (CH1) during switch. enter image description here

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  • \$\begingroup\$ Is the pop a DC pop or a pop due to a sudden change in the audio signal. i.e. Are you muting your guitar while switching or are you switching while playing. \$\endgroup\$
    – Transistor
    Commented Sep 23, 2019 at 19:49
  • \$\begingroup\$ The pop is present whether the guitar is muted or not however in our application, we will be switching while playing. Its basically a single channel effects loop switcher. \$\endgroup\$
    – Ryan Jaquin
    Commented Sep 23, 2019 at 19:51
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    \$\begingroup\$ I'm betting on charge injection. \$\endgroup\$
    – bobflux
    Commented Sep 23, 2019 at 21:00
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    \$\begingroup\$ those switches pump charge when switching, they will always pop. use photoresistor or JFET gates for noiseliess switching. \$\endgroup\$
    – Jasen Слава Україні
    Commented Sep 23, 2019 at 21:04
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    \$\begingroup\$ photoresustors can switch slowly, and as they proivide galvanic isolation will not inject any charge into the signal path. jusr drive it with a LED. you can parallel the LED with a capacitor to further reduice switching speed. \$\endgroup\$
    – Jasen Слава Україні
    Commented Sep 25, 2019 at 1:22

1 Answer 1

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Page 13 of the ADG1419 datasheet, figure 28 reads \$Q_{INJ} = C_{L} × ∆V_{OUT}\$. Charge injection is specified on page 4 as 13 pico-Coulombs, which isn't much, but must be enough to do what you are seeing. So this formula is saying that the amount of injected charge is the product of the output capacitance and voltage swing.

To reduce the effect of charge injection from this chip, decrease the output capacitance \$C_{L}\$ on the output pin 1 AU_OUT (perhaps add a unity-gain op-amp buffer right after this chip with a tiny input capacitance.) And if you can, decrease \$∆V_{OUT}\$ which means decreasing the 7.5v rail the chip is powered from.

Unlike a FET switch, this device most likely cannot be "slowed" to produce a noise-less switch.

However, the duration of the glitch is around 4µs, and 4µs corresponds to a frequency of 250kHz. If your audio content only extends to 20kHz or so, placing a 20kHz low-pass filter after the switch may completely remove any glitches.

Another (brute-force) option could be to add a transistor which pulls the output strongly to the signal's reference voltage. Turn this "clamp" transistor on and flip the source switch simultaneously, then turn the clamp off 1µs later. The clamp will absorb the majority of the charge injection, and lasting only 1µs, the lack of output may not be noticeable.

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  • \$\begingroup\$ Thank you so much for this information. How would we implement something like your last suggestion with a clamp transistor? What transistor would work for that and how would we sync it up with the control switch (SW_SET)? \$\endgroup\$
    – Ryan Jaquin
    Commented Sep 26, 2019 at 19:54
  • \$\begingroup\$ I would try a simple passive R-C lowpass filter first as that is easy. Insert a 750Ω resistor into AU_OUT. Tie the end furthest from the ADG1419 to a 10nF cap, and the other end of that cap to audio ground. That should dampen a 250kHz pulse by about -20dB. \$\endgroup\$
    – rdtsc
    Commented Sep 26, 2019 at 21:35
  • \$\begingroup\$ What is SW_SET's voltages? 0-5v? Are the audio signals biased (DC offset) around a certain voltage, such as 2.5v? \$\endgroup\$
    – rdtsc
    Commented Sep 26, 2019 at 21:43
  • \$\begingroup\$ SW_SET is 0-3.3V The audio signals are not biased. \$\endgroup\$
    – Ryan Jaquin
    Commented Sep 30, 2019 at 19:10
  • \$\begingroup\$ The audio should be DC-biased; likely centered around 1/2 of Vcc which might be 7.5v/2 =3.75v. If the audio has a DC bias of 0v, or if the bias of AU_IN1 and AU_IN2 differ, that alone will cause a pop sound. \$\endgroup\$
    – rdtsc
    Commented Oct 1, 2019 at 20:07

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