I have a circuit to power some 5-volt logic from a +24VDC source. It has some basic reverse-polarity protection and uses a TI 5VDC LDO.
It all works great during normal operation however, when I use my FLUKE multimeter in amp mode to test the current draw like so:
The LDO blows up immediately. Smoke, sparks, a bright light, all of it. Anyone know what's going on?
Thanks
I think people are distracted by the PMOS, but the real reason is a voltage spike when the 24V is connected, due to inductance of the wiring that is even higher when the multimeter is connected, vastly exceeding the max voltage of the LDO. I assume you are using a ceramic capacitor at the LDO input, which is a reason someone may be experiencing this problem for the first time -- it wouldn't happen with an electrolytic cap, as I'll explain.
Forget the transistor for now and model the circuit like this, with a source that has some resistance and inductance in the wiring (R1, L1). Also model the capacitor as having a very low ESR (R2):
simulate this circuit – Schematic created using CircuitLab
Simulate this and you'll see that the RLC circuit rings, peaking at about 42V when the 24V turns on:
Now try the same thing after changing R2 from 10 mΩ (which could be a typical ESR for a multilayer ceramic capacitor) to 1 Ω (which could be a typical ESR for an electrolytic capacitor) and the peak will be much lower, about 27V:
The added resistance in series with the cap significantly dampens the oscillation, keeping the input voltage well with range of the LDO. Yay! So the simple solution is to add an additional 1 Ω resistor between your 1 uF capacitor and GND to account for the low ESR of the cap.
You should be able to observe this behavior in the real circuit pretty easily with an oscilloscope. Remove the LDO (to avoid blowing it up) and watch the voltage across the capacitor when you first attach the 24V. You can tweak the value of the added resistor as necessary to ensure the peak never goes above the LDO's limit.
Alternately, the ringing will never exceed twice the input voltage regardless of any of the parasitic values, so you could switch to a LDO that has a >48V input limit and you'd always be safe.
I agree with VillageTech in incriminating the PMOS. It has a capacitive load in the source and an inductive load in the drain (your mutlimeter wires), add a bit of parasitic inductive/capacitive coupling and you get a colpitts oscillator.
However, since your supply is 24V and you're using a LDO to make 5V at 80mA, I wonder why you need to use a PMOS to make a quasi-ideal low dropout diode...
If you implement your reverse polarity protection with a dumb old diode, dropping 0.6V, the LDO will still have 18.4V headroom instead of 19V!
So I'd say just get rid of the PMOS and replace with a diode.
If the PMOS provides reverse polarity protection for other stuff on the 24V rail that you didn't mention in your question, then of course don't remove the PMOS, but instead add a cap on the 24VDC input. Preferably an electrolytic with a bit of ESR, like a 10-100µF general purpose cap, to damp transients or resonances due to cable inductance and low-ESR caps in the power supply. A low-ESR ceramic cap may produce ringing due to this.
I'm suspicious that you may have insufficient capacitance on the output of the LDO. Personally, I think it unlikely the MOSFET is involved in this, the body diode severely limits what mischief it can get up to.
If the LDO is hovering on the edge of instability, a small change to the input could push it over the edge. If you're using a very small (physically) capacitor, the capacitance under bias may be much less than even the nominal 1.5uF you've shown. And you're under the recommended minimum 2.2uF even with the nominal value.
But that may not be the main thing wrong. Consider the massive power dissipation for such a tiny device, as Andy points out. If I read the suffix code correctly you have an SOT-23-5 device, which has a datasheet (possibly optimistic, depending on the footprint) junction-to-ambient thermal resistance of 212°C/W meaning at room temperature the junction is heading for 350°C. FAR too high for a silicon chip. Now, it's supposed to shut down gracefully under thermal overload (at a very high die temperature), but that's not a good thing to provoke and with such a high input voltage it may well be dying as a result.
It seems that your PMOS protection circuit starts oscillating because of adding long wires (inductance) in series to power source. Try to add 0.1uF capacitor between drain of PMOS (pin 3) and ground.
The 50v input capacitor will survive a spike above 30v, which I is fatal to the regulator.
You may have an over voltage spike at power up.
It is possible that at power up, an inductor present in the ammeter tries to overrun the stabilizing inrush current, thus raising the voltage beyound the capability of the regulator. So as soon as the inrush current falls back to stable value, the ammeter reacts by raising the voltage, effectively acting as a booster. It has little energy but enough voltage over 30v to fry the regulator while the input cap is protected up to 50v, which apparently is never achieved.
Sometimes the industrial 24vdc power supplies are adjustable up to 28 or even 32vdc. Make sure yours is set to 24vdc.
The input cap (50v) needs discharged at power down. If you disconnected the load, then powered down to insert the ammeter, you kept the capacitor charged, thus prone to carry a spike should one occur.
This not an easy troubleshooting. The starting point should have been the 24vdc supplied, so close to max 30v supported by the regulator.
