I am looking for design advice with a one-off Radar interface:

  • A RF video signal (Radar signal envelope) has to be sampled at 40 MHz
  • X datapoints in succession
  • triggered at 820 Hz
  • transfer of data after each acquisition sequence to a PC via USB

design constraints:

  • one-off design
  • minimal RF PCB design

My starting point would be:

  • a 40 MHz ADC -> requires 40 MHz clock & parallel datainterface to avoid high frequency circuits
  • SRAM to store at lease one acquisition sequence of X datapoints
  • microcontroller with USB interface


  1. Is there a better way to approach the problem?
  2. What is the easiest way to control the acquisition sequence, i.e. to transfer the data from ADC to SRAM? This obviously cannot be controlled by the MCU and I would like to avoid having to learn FPGA programming. Are there any ready-made solutions?
  3. What is the best way to get the data from the SRAM to the MCU? The parallel interface would require either a high pin-count or a serial converter that knows about SRAM read-cycles. Again: what is the best solution?

Many thanks.


2 Answers 2


The big unanswered question is what bit resolution (and implementation noise figure) you need.

In the unlikely case that this is limited to around 8 bits, you are basically looking at a digital sampling oscilloscope front end.

In the more likely case that you want 14-16 bits, you are looking at a wideband software defined radio sampler, though without the usual continuous reception requirement.

Lots of designs for both are available - mostly consisting of an ADC, an FPGA of some sort, potentially an outboard buffer memory, and a USB interface. For a one-off, you'd be better of buying than building, unless the learning experience of doing it yourself is a higher priority than the cost, timeliness, and capability of the result.

If you go with an SDR front end, you may need one that can be customized, since your bandwidth may exceed the continuos streaming capability - instead of the normal decimation to a lower bandwidth (and higher resolution) before streaming, you might instead want to do periodic snapshots at full bandwidth, which could necessitate an FPGA code change. This would point towards some of the open source platforms over proprietary ones, unless you find one already made for burst usage.

  • \$\begingroup\$ 8 bits are more than ok and any common noise figure should be ok. This is not a high-precision application as the signals are pre-processed and amplified. It is only a matter of digitisation. I was not aware of digital sampling oscilloscope front ends as a ready-made product. Can you by any chance provide an example link? \$\endgroup\$
    – ARF
    Nov 29, 2012 at 19:08
  • \$\begingroup\$ "PC oscilloscope" or "USB oscilloscope" may get you search results. But beware of odd data interfaces that might be hard to integrate into a custom application. You may want to look for something that has an open firmware, at at least open PC-side drivers. Still, if you want to do much more than gross ranging you may need more amplitude resolution. \$\endgroup\$ Nov 29, 2012 at 19:16
  • \$\begingroup\$ OK, I did not realize you were taking about the cheap mini-oscilloscopes that have begun to appear. Regarding resolution: The idea is to get the radar image from a consumer-grade marine radar scanner onto a PC. The usual display seems to do 4 bit conversion of the signal for display on a (16 level?) grey-scale LCD display. (Unless I am reading the schematic wrong.) Is wanting to do more than simple ranging realistic if the scanner does not have a actively shaped emission wave form? \$\endgroup\$
    – ARF
    Nov 29, 2012 at 21:09
  • \$\begingroup\$ Are you going to be sampling the IF, or the output of a power detector/AM demodulator? At a minimum, I'd consider that you might want enough resolution to be able to do a log transformation before display. Also, what is the minimum range of the system as determined by receiver blanking after the transmit pulse? If it's substantial, 40 MHz sampling probably gives you a useless timing resolution, though if you are sampling an IF to demodulate in software, then you would need that bandwidth. \$\endgroup\$ Nov 29, 2012 at 21:14

For a one-of design, it makes more sense to put more effort into the overall system spec and buy an inexpensive DSO to do the acquisition.


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