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This is my first time posting on this board, so I am a little unfamiliar with what I am supposed to put in my question. The sequence I have to detect is 1010... including the overlaps. I am using LTspice to simulate the circuit and am primarily interested in proving that the circuit works by means of the waveform plot. The schematic for the design I came up with is as follows:

enter image description here

x is the input signal which is 1010....

The waveforms that I get look like this : enter image description here

(green = clock, blue = input signal (1010...) and red = output)

which I am confused about because the output shows spikes , whereas I am expecting a sustained square pulses for 1 complete clock cycle. But the spikes appear at the right places (when the input sequence has completed 1010)

In summary, I have two questions

  1. Am I setting the voltage sources to the correct values for the purposes of this demonstration ?
  2. If yes, then why am I getting spikes instead of a square pulse till the next clock edge ?

I will admit that I have a very basic working knowledge of LTspice so if I am doing something wrong I am more than happy to learn thanks! Following is the netlist:

XU1 N002 clk N004 NC_01 D_FF
XU2 x clk N005 N006 D_FF
XU6 N004 x N006 N003 AND_3
XU7 N003 N001 N002 OR_2
XU4 N001 N004 y AND_2
XU3 N005 N007 N001 AND_2
XU5 x N007 INV_1
V§clock clk 0 PULSE(0 5 1ns 1ns 1ns 1ms 2ms)
V2 x 0 PULSE(0 5 1ms 1ns 1ns 2ms 4ms)
.tran 20ms
.lib DigitalLogic.lib
.backanno
.end

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    \$\begingroup\$ Exclude the input which from the output and just gate the register outputs. Another way is use /2 FF and XOR with data then sample on alternate clock edge to avoid race. \$\endgroup\$ Commented Mar 30, 2021 at 22:01
  • \$\begingroup\$ Thanks. Thats one thing I never really considered. The only thing reason I used the output (Bx') is so I could reuse that value. \$\endgroup\$
    – First User
    Commented Mar 31, 2021 at 4:45
  • \$\begingroup\$ @Tony Update: I used a D flip flop to divide the clock frequency which I fed to the circuit instead of x and it seems to be working. I havent yet read about race conditions so I am unaware of how exactly this works but I will be keeping this in mind in the future thanks! \$\endgroup\$
    – First User
    Commented Mar 31, 2021 at 5:01

1 Answer 1

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I was curious to try your circuit and also got spikes, but I avoided spike by adding delay to AND gate with Y output. Also it seems you are using custom digital library, so it's not clear what parameters the components have.

Seems like comment made about alternative implementation could simplify design.

A2 X 0 clk 0 0 N006 N005 0 DFLOP Vhigh=5 Vlow=0 Td=20n Trise=10n tripdt=5n
V1 X 0 PULSE(0 5 1m 5n 5n 2m 4m)
V2 clk 0 PULSE(0 5 5n 5n 5n 1m 2m)
A3 0 N005 0 N007 0 0 N002 0 AND Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A7 N003 N002 0 0 0 0 N001 0 OR Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A8 X 0 0 0 0 N007 0 0 BUF Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A1 N001 0 clk 0 0 0 N004 0 DFLOP Vhigh=5 Vlow=0 Td=20n Trise=10n Tfall=10n tripdt=5n
A4 N002 0 N008 0 0 0 Y 0 AND Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A5 N004 X N006 0 0 0 N003 0 AND Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A6 N004 0 0 0 0 0 N008 0 BUF Vhigh=5 Vlow=0 Td=20n Trise=10n tripdt=5n
.tran 20m
* Tfall is by default equal to Trise\nRef is by default (Vhigh-Vlow)/2\nSee "A. Special Functions" in help docs
* Added delay to this input to avoid spikes
.backanno
.end

Schematic

Edit: I would emphasis that although one delay at output seemed to fix spike issue. That is not guarantee this circuit works with other sequence of 0's and 1's. I believe the issue here is that when the inputs transition from logic low to high (or high to low) there can be undefined state at transition time. The direct feedback also complicates things as comment suggests.

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    \$\begingroup\$ Please emphasize somehow the paragraph with the solution by adding a delay. You could also add that direct feedback causes the states to end up in a paradox: the output depends on the input, the output changes, but implicitly so does the input, which had the previous state because of the past input, and that can cause confusion. Also a minor note: tau (or Rout/Cout, or Rhigh/Rlow/Cout) is better behaved than trise/tfall, unless your application requires a linear rising/falling time. This is not the case, though that's not to say they can't be used. \$\endgroup\$ Commented Mar 31, 2021 at 7:47

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