I am working on a new project that seeks to implement a three-stage audio amplifier. One of my stages consists of a CASCODE circuit using the BF998 NMOS transistor. For this stage I am struggling to mathematically build a circuit using this transistor and generate a gain with a specific harmonic distortion.
- Initially I have chosen a region of operation for my circuit. By observing the graph Id x Vgs, I noticed that Vth is approximately -0.6 V and I chose to operate at VGS=0.1 V (Consider my input signal equal to approximately 260 mV)
- My output impedance (other stage) is equal to 2367 Ω. Therefore, I have determined the minimum current required to keep my signal from clipping (Iout= 1.4364 mA)
- Furthermore, I used a resistor bias and considered that the current passing through the resistor branch is 2000 times smaller than the current passing through the drain of the common gate.
From this, I don't know how to control the gain and set harmonic distortion for this stage. I would like to learn how to design these two quantities with mathematical relationships and then implement the circuit in Advanced Design System (ADS). What I have built so far can be seen in the image below:
For additional questions, I am always available to answer them. I am very interested in learning how to design this stage of my project.