1
\$\begingroup\$

enter image description here

I am designing an ADC driver (20-bit differential ADC) with an input signal range from 0-10kHz, sampled at 1Msps and with 1 LSB of 47uV. I choose 1Msps rate for oversampling factor of 10.

Referring to my quick sketch (showing only one driver side for a bipolar ADC), the buffer configuration is obviously the simplest one, but the op-amp 90Mhz bandwidth means full bandwidth noise present on the op-amp output. However, with 5nV/sqrt(Hz) input noise op-amp, and using an additional RC filter on the ADC input (f-3db ~= 2.5Mhz) the total calculated noise is well under 1 LSB or about 12uV

In the second setup, with 10Khz LP filter the total calculated noise is <1uV. All components including the capacitor are matched to 0.1%

Do I really have the benefits of lower noise with the second setup or I just ask for more trouble with more components on the PCB around the op-amp with possible leakage currents and cross-talks with other traces running around, and not to mention that any mismatch among components will decrease CMRR of an ADC?

\$\endgroup\$
2
  • \$\begingroup\$ What ADC are you using? \$\endgroup\$
    – Voltage Spike
    Jun 23, 2021 at 17:10
  • \$\begingroup\$ LTC2378-20 | *edit 1 LSB is =9.5uV \$\endgroup\$
    – Mr No
    Jun 23, 2021 at 17:32

1 Answer 1

1
\$\begingroup\$

The first setup will have a lot more noise, because the filter pole is set at ~5MHz (I can't read it, its cutoff, but I'm assuming 100Ω and 330pf) and the noise contribution from the opamp (which has ~5nV/sqrt(Hz)), the second setup has a gain of 2.5 and bandwidth of 10kHz.

The opamp calculation for white noise is:

Opamp white noise * sqrt(BW of analog system)= noise in Vrms

So to find a rough cut number (not factoring 1/f noise) for the total noise contribution from the white noise of the opamp there would be:

5nV/sqrt(Hz)*sqrt(5MHz)= 11uVrms

The noise figure from the second would be about:

5nV/sqrt(Hz)*sqrt(10kHz)= 0.5uVrms

But it also is gained up so the noise would be also to about 1.25uVrms

One rule of thumb for designing analog systems minimize the bandwidth of the system, and maintain that bandwidth to the ADC.

\$\endgroup\$
4
  • \$\begingroup\$ Thanks, that is about the same as my calculations and I agree that the second setup is better from a noise perspective. \$\endgroup\$
    – Mr No
    Jun 23, 2021 at 19:23
  • \$\begingroup\$ meta.stackexchange.com/questions/126180/… \$\endgroup\$
    – Voltage Spike
    Jun 23, 2021 at 19:31
  • \$\begingroup\$ .. to add. In almost every fast SAR ADC datasheets for fast settling time are used wide bandwidth buffer op-amps. I often see >200Mhz op-amps being used as buffers with 20bit ADCs \$\endgroup\$
    – Mr No
    Jun 23, 2021 at 19:37
  • \$\begingroup\$ Also you may want to check out: analog.com/media/en/technical-documentation/data-sheets/… which I believe is based off of the same SAR core, figure 9 It's how to pipe in low freq to these fast SAR cores (the 2508 was the first one in the family, all of the other SAR's in this famliy have a different decimating\filtering backend.) \$\endgroup\$
    – Voltage Spike
    Jun 23, 2021 at 19:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.