0
\$\begingroup\$

How do high speed digital transceivers which do not share a common clock synchronize? Particularly ones which do not have an ADC front end?

Would you just oversample the signal using a digital input, essentially a 1 bit ADC? It seems this would be likely to glitch.

To give an example, USB 2 HS which runs at 480 Mbps, doesn't appear to have a front end ADC but it does send a preamble which leads me to believe the receiver is sampling at a rate higher than the bit rate.

\$\endgroup\$
5
  • \$\begingroup\$ You keep referring to ADCs but these are digital circuits, albeit with an analogue signal conditioning circuit at the front end. Disregard the idea of ADCs in this analysis. I don't know if you have a primarily analogue background and less so on digital but it reads that way. Although a digital input can be viewed as a 1-bit ADC, it's not useful or advantageous to do so here and rarely so in digital communications. Digital electronics itself is indeed just convenient analogue, and not a separate entity, but it's not relevant in this analysis. \$\endgroup\$
    – TonyM
    Commented Jan 5, 2022 at 9:39
  • \$\begingroup\$ Won't digital signals which are over sampled be likely to glitch? \$\endgroup\$ Commented Jan 5, 2022 at 16:28
  • \$\begingroup\$ Cryptic one-line questions won't get answers. It's not a free personal help centre. You, the OP, has has to do the work. Write a detailed argument with a point with information to substantiate it. \$\endgroup\$
    – TonyM
    Commented Jan 5, 2022 at 16:30
  • \$\begingroup\$ The point is, digital inputs aren't normally filtered to correct signals in the indeterminate voltage range. I guess a comparator with a Schmidt trigger could be used. \$\endgroup\$ Commented Jan 5, 2022 at 16:49
  • \$\begingroup\$ First, yes, digital signals can be digitally filtered to reject the indeterminate range. It's done all the time, I do it all the time. Qualify your argument there. A Schmitt trigger is a bonus. Secondly, please can you stop now and edit your question to explain your own background and skills and then to detail your question. You seem to want this to be a discussion forum and it's a Q&A site. \$\endgroup\$
    – TonyM
    Commented Jan 5, 2022 at 17:06

2 Answers 2

1
\$\begingroup\$

The key is that although the devices do no share a common clock, they each have their own similar clocks. Although these clocks are not the same, they have a specified frequency with some tolerance.

When the transmitter sends a message, the receiver uses the preamble to determine the frequency offset between the sender clock and its own clock. The receiver uses this information to perform frequency and phase synchronization, often in the form of a digital PLL.

Sampling at more than one sample per symbol can make synchronization more reliable, although the main advantage to doing this is to perform symbol timing synchronization, so you are usually sampling near the center of the symbol.

I don’t know the specifics of USB2, but most communication channels perform frequency and timing synchronization of some sort, and a preamble gives the receiver a chance to figure out the frequency and timing of the transmitted signal so it can synchronize before the data begins.

\$\endgroup\$
0
\$\begingroup\$

If you are wondering about USB specifically, the specs are freely available for you to read how it works in detail.

In short, any serial data stream sent without a separate clock is not sent blindly as just raw data bits one bit after another, but encoded with a line code or framed with a protocol which ensures that there is enough transitions to help the receiver to recover the clock or regenerate it and keep the receiver synchronized to the bit stream.

Essentially such encoded streams can be said to contain embedded clock or be self-clocking.

The line code may also contain special symbols or bit patterns that can be used to determine for example which bit is the first bit of a byte or frame.

For example USB3 uses 8b/10b line coding transmit data.

\$\endgroup\$
6
  • \$\begingroup\$ But is the receiver over sampling? I don't think there is an adc in front so does it oversample the digital signal? \$\endgroup\$ Commented Jan 5, 2022 at 7:59
  • \$\begingroup\$ @FourierFlux, please refer to my comment on your question. \$\endgroup\$
    – TonyM
    Commented Jan 5, 2022 at 9:39
  • \$\begingroup\$ Why would it oversample? There is no need for that. It might still be possible to oversample, but there can be no general "yes" or "no" as different high speed receivers may have implementation specific mechanisms to receive a certain specific stream. \$\endgroup\$
    – Justme
    Commented Jan 5, 2022 at 10:55
  • \$\begingroup\$ Why would it oversample? There is no need for that. Asynchronous digital serial data receivers like USB's will obviously oversample the input stream, so they can align themselves to the centre of the 'eye' where the data is stable, away from transitions. All those USB devices around you are doing just that. A better question is what made you think they weren't? \$\endgroup\$
    – TonyM
    Commented Jan 5, 2022 at 11:29
  • \$\begingroup\$ @TonyM So for some reason, of all the possible clock data recovery mechanisms, all USB devices must use or happen to use the oversampling method? Sure oversampling is possible for low speed and full speed, but for 480 Mbps or several gigabits too? \$\endgroup\$
    – Justme
    Commented Jan 5, 2022 at 13:20

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.