Unexpected impedance spike when paralleling capacitors

Question

I was watching a video from EEVBLOG about bypass capacitors, and he presented a theory that randomly connecting different values of capacitors in parallel can create unexpected impedance spikes:

To inspect the picture, right click and open in new tab, the scales are then visible. Regardless: The frequency scale is logarithmic, impedance scale is linear. Both graphs have 100kHz-40MHz frequency range, and the spike on the left side is located at 8Mhz point, reaching ~800mOhm impedance.

He did not explain why the spike is there. Thinking about it some more, I could not come up with an explanation other than bad test setup. Resistance and inductance go down as more values are added in parallel. Although total capacitance goes up, which would lower the total resonance frequency, 110nF in relation to 10uF cannot cause such a drastic shift.

This was his test setup:

I assume that the solder blobs between capacitors introduced a series inductance that in turn caused the spike in impedance at 8MHz.

Could that be the case, or is there something else that could cause the spike?

Answer 1

This is called "antiresonance" and it is an important part of designing in the decoupling caps for your chips.

The caps themselves have inductance and resistance. In addition, the PCB, adds inductance depending on how they are mounted, if they are connected with traces, vias, planes, etc. I eyeballed the mounting inductance and used some typical ESR/ESL values, and I get an impedance peak around the same frequency. The plot on the left shows the impedance of both caps in parallel.

To calculate this...

Notice the two caps and their L and R form a series RLC network. I simplified it in the above schematic. First, all the inductances are in series, so I added them into one single inductor (left). Then, all the resistances are in series, so I added them into a single resistor (middle). And the two caps appear in series, so I calculate the resulting capacitance (right). So we get a series RLC network with 99nF, 55mOhm, and 6 nH. The resonance frequency is \$ \frac{1}{2 \pi \sqrt{ LC }} \$ which is about 6.5MHz. That corresponds to the peak in the impedance plot.

If the two caps have the same value, then the impedance peak disappears (right schematic, red trace)... but only if one forgets to model the inductance of the trace connecting them!

So, to summarize:

If you use close coupled power and ground planes, you can parallel capacitors with very low inductance between them. Then, you can use lots of capacitors (and lots of work) to design a flat impedance power rail. A smaller version of this is a power island under a chip, coupled to the ground plane, with a bunch of caps on it. The key feature is low inductance between the caps, which allows wiring them in parallel without too much trouble. But close coupled planes are expensive, because you need 6 layers. On a 4 layer board, you can get good coupling between the outer layer pairs because they're only 0.2mm from each other, so it works very well to make small power islands under the chips.

When using planes, since the inductance between caps is very low, you can use larger caps, with larger package, and therefore larger inductance for low frequency decoupling, and smaller caps with smaller packages and therefore lower inductance for high frequency decoupling. Basically, the low inductance of the plane doesn't add too much to the low inductance of a smaller cap.

However, if you use a 2 layer board, or a 4 layer but without close coupled planes, then paralleling capacitors can become a bit hazardous because the traces connecting them together will add enough inductance to create antiresonance peaks. Sometimes they are surprisingly high and introduce a lot of noise into your power rail.

In this case, lower value caps like 100nF work pretty well because their built-in ESR is a bit high, which dampens the resonance. If you make a board with a microcontroller and a bunch of logic chips, put in a good ground plane, route power with traces, and place 100nF on every power pin... it's quite bulletproof.

However you might find that adding one 10µF ceramic cap actually increases the noise, because these have very low ESR, so they make higher Q peaks. Sometimes, an electrolytic with a bit of ESR results in more damping, therefore less noise.

In addition, if both caps are the same size, like 0805, they will have the same inductance. As far as MLCCs are concerned, inductance depends pretty much only on size. So if you see a 100nF and a 10µF next to each other, both in the same 0805 package... then the 100nF isn't actually doing anything useful.

Answer 2

The electrically larger capacitor is usually physically larger, which means longer leads, which means significant series inductance.

At high frequencies, above the series resonance of the bigger capacitor, it will look inductive.

You now have a parallel circuit of the large capacitor's inductance and the small capacitor's capacitance, which will resonate, producing a high impedance.

This is a real problem, yet several well-respected companies still put the advice 'use several caps of different sizes in parallel' in their application notes. Why I don't know. As an RF engineer, I have often come across problems which were fixed by fixing this unwanted bypass capacitor resonance.

In real circuits, this doesn't cause trouble as often as one might expect it to, given its common (mis)use. Why not?

• The circuit has to produce an unwanted signal at the resonance frequency, which then has to interfere with another part of the circuit, or escape as measurable EMI, to cause trouble.
• Low Q capacitors, like aluminium with their high ESR, make the resonance less severe than it would be with all ceramics.
• Resistance in the tracks, or intentional series resistors or ferrite beads that people often use between these capacitors, will often reduce or kill any resonance.

Answer 3

I think you can make a pretty good case for the spike being caused by the addition of the 100n and 10n capacitors: -

I assume that the solder blobs between capacitors introduced a series inductance that in turn caused the spike in impedance at 8MHz.

It can't be ruled out but neither can the inductance of the yellow, orange and green wires on the test set-up. I mean, where do they go and what effect do they have I wonder?