NOR flash ignores dummy cycle config (gd25b512)

Question

I have existing code on a STM32F7 using qspi for a micron MT25QL512ABB that I am porting to use on a Gigadevice GD25B512ME. I am operating the bus at 108 MHz.

The issue I'm facing is that the gigadevice specifies a dummy cycle setting of 10 for > 104 MHz on the 7.3 table (page 21), but the setting seems to be ignored on all fast read options, rather defaulting to 8 dummy cycles. I'm a little dubious about the reliability of operating outside of spec, and it seems odd that the device would ignore this setting. Table 13 on page 22 lists an 8 dummy cycle default for standard SPI, and 6 cycles for QSPI, which isn't what is happening, rather 8 for QSPI mode.

I'm setting the cycles by Read/writing instruction 0xB5/0xB1, address 0x01, reg value or'd with 0x02.

As a reality check, am I missing something core here, or do I just chalk this up to an incomplete datasheet written in hard times?

GD25B512ME datasheet
MT25QL512ABB datasheet

Answer 1

This device apparently ignores the nonvolatile 0xB1 command, the 0x81 command has to be used instead. For bonus points, it also ignores the 0x50 WEL latch mentioned in the data sheet, requiring the standard write enable command.