Will PCIe Host issue configuration read / write type of transaction other than the enumeration phase?

Question

With my limited understanding, the PCIe end point and it's feature capability will be discovered by the host during enumeration phase. Hence, I believe most of the configuration type of write and read operation initiated by the host will be communicated through the PCIe link.

I'm wondering that after the enumeration phase is done, is it common that the host still send config read / write type transaction to the endpoint or device.

Or probably, some features from end point that not discovered by the PCIe host during enumeration phase will be discovered in the later time through certain approach?

Answer 1

It's possible.

Configuration reads/writes are used to access configuration registers. These registers are required for enumeration, but they are also useful for power management configuration or error information, and a device can have custom registers for any purpose.

Answer 2

Absolutely. Most things that live in config space will not be handled during enumeration. During enumeration, the main things that need to be addressed are bus number assignments and BAR allocation. Pretty much everything else can be done later under the direction of the device driver.

So, for example, when the driver is loaded for a device that supports MSI, then the driver can request that the operating system set up some number of MSI channels on the device. The address and data values, number of MSI channels active, and the MSI enable bit are all located in the MSI capability in the config space, so configuring MSI will require config read/write operations.

Similarly, if a device uses DMA, then the driver needs to set the bus master enable bit in config space, usually after doing some amount of initialization. Since this also lives in config space, config read and write operations are required.