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With my limited understanding, the PCIe end point and it's feature capability will be discovered by the host during enumeration phase. Hence, I believe most of the configuration type of write and read operation initiated by the host will be communicated through the PCIe link.

I'm wondering that after the enumeration phase is done, is it common that the host still send config read / write type transaction to the endpoint or device.

Or probably, some features from end point that not discovered by the PCIe host during enumeration phase will be discovered in the later time through certain approach?

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2 Answers 2

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It's possible.

Configuration reads/writes are used to access configuration registers. These registers are required for enumeration, but they are also useful for power management configuration or error information, and a device can have custom registers for any purpose.

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  • \$\begingroup\$ Thanks! You mentioned the important point which is the custom register set for any purposes from the endpoint / device. In fact, this is the main purpose of my question above. Let's say the custom register set is not discovered by host during enumeration phase, then what make the host can or go to discover it in later time? \$\endgroup\$
    – Learner
    Oct 12, 2022 at 16:29
  • \$\begingroup\$ The custom driver for that custom device would know about them. \$\endgroup\$
    – CL.
    Oct 14, 2022 at 13:53
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Absolutely. Most things that live in config space will not be handled during enumeration. During enumeration, the main things that need to be addressed are bus number assignments and BAR allocation. Pretty much everything else can be done later under the direction of the device driver.

So, for example, when the driver is loaded for a device that supports MSI, then the driver can request that the operating system set up some number of MSI channels on the device. The address and data values, number of MSI channels active, and the MSI enable bit are all located in the MSI capability in the config space, so configuring MSI will require config read/write operations.

Similarly, if a device uses DMA, then the driver needs to set the bus master enable bit in config space, usually after doing some amount of initialization. Since this also lives in config space, config read and write operations are required.

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