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Why are there two collector resistors in the first circuit but in the second circuit there is only one?

What is the difference?

When there is only one collector resistor, does this affect behavior?

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  • \$\begingroup\$ Heroz, One difference is that in the top circuit it is possible to saturate either BJT if RE provides enough current (the common mode voltage is high enough) while in the bottom circuit Q1 cannot be saturated, while Q2 still technically can be. Another is that in the top circuit the Early Effect will apply in similar symmetry to each other in both BJTs while in the bottom circuit the Early Effect will no longer apply with such symmetry. THere's more but those two things stand out to me at first glance. \$\endgroup\$
    – jonk
    Commented Nov 3, 2022 at 18:06
  • \$\begingroup\$ Heroz, if we are done here, please take note of this: What should I do when someone answers my question. If you are still confused about something then leave a comment to request further clarification. \$\endgroup\$
    – Andy aka
    Commented Nov 6 at 10:28

2 Answers 2

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In the first circuit there are two outputs therefore there has to be duplicated collector resistors. This type of circuit is a differential output type. In the 2nd circuit there is only one output hence there only needs to be a single collector resistor associated with that output. It has a single-ended output.

When there is only one collector resistor, does this affect behaviour?

For the single-ended output type, not dramatically.

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At the risk of over-simplifying, the transistor collectors are essentially current sources. So the collector resistor (RL in the upper diagram) has no effect on the rest of the circuit.

RL is there as a current to voltage converter thus allowing an output voltage to be passed to the next stage.

If a differential output is required, then each collector will require an RL.

If a single ended output is required then only one RL is required making the lower circuit diagram a differential to single ended converter, a common task for the input stage of an op-amp.

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