0
\$\begingroup\$

Based on this online resource, KeyE M.2 has

2x PCIe x1 / USB 2.0 / I2C / SDIO / UART / PCM

Their pinout table shows these lanes (for E-key):

35 PETp0
37 PETn0
41 PERp0
43 PERn0
47 REFCLKp0
49 REFCLKn0
50 SUSCLK
52 PERST0
53 CLKREQ0
55 PEWAKE0
59 Reserved/PETp1
61 Reserved/PETn1
65 Reserved/PERp1
66 PERST1
67 Reserved/PERn1
68 CLKREQ1
70 PEWAKE1
71 Reserved/REFCLKp1
73 Reserved/REFCLKn1

I successfully managed to install an M.2 (M-key) SSD into a keyE slot with an adapter, by interconnecting the above KeyE pins with the SSD (M-keying):

  KeyE         KeyM
-----------------------
35 PETp0      49 PETp0
37 PETn0      47 PETn0
41 PERp0      43 PERp0
43 PERn0      41 PERn0
47 REFCLKp0   55 REFCLKp
49 REFCLKn0   53 REFCLKn
53 CLKREQ0    52 CLKREQ
55 PEWAKE0    54 PEWAKE
50 SUSCLK     68 SUSCLK
52 PERST0     50 PERST

Now, the NVMe SSD is perfectly recognized by Linux, however, I just have realized that there is another PCIe on the KeyE slot.

Can I utilize this (pins above 58 on KeyE) other PCIe to make the NVMe SSD faster?

Currently it's downgraded (due to 1x PCIe) (lspci output):

LinkSta: Speed 5GT/s (downgraded), Width x1 (downgraded)

Can I interconnect KeyE's PCIe1 to KeyM's PCIe1?

I can only connect these:

  KeyE         KeyM
-----------------------
59 PETp1      37 PETp1
61 PETn1      35 PETn1
65 PERp1      31 PERp1
67 PERn1      29 PERn1

Or I have to somehow configure (synchronize) PCIe1's clocks and controls (REFCLKp1, REFCLKn1, CLKREQ1, PEWAKE1, PERST1) to control PCIe0's clocks and controls?

\$\endgroup\$
2
  • \$\begingroup\$ It's unlikely that the mainboard even provides these signals in the first place. \$\endgroup\$ Commented May 6, 2023 at 18:26
  • \$\begingroup\$ I think you are right, there seems to be only one lane populated from the CPU. I still leave this question open, it's rather interesting to know whether is grabbing 2 PCIe x1 lanes to one PCIe x2 even "in theory" possible. (And if so - how?) \$\endgroup\$
    – Daniel
    Commented May 6, 2023 at 19:13

1 Answer 1

2
\$\begingroup\$

As the secondary PCIe pins are optional, there is no guarantee that they are even wired up.

Even if they were, it is generally not possible to combine multiple PCIe links into a single one.

To be able to aggrigate the lanes from different links into a single link both the upstream port and BIOS/EFI/Firmware would have to support this, which would only be possible if the two links were bifurcated in the first place (i.e. they were originally a larger link split up into seperate links).

About the only reasonable thing you could do to speed things up in the highly likely case that aggregation is not supported, would be to use two SSDs, and form a striped RAID array. This would split accesses across the two drives to hopefully increase the overall transfer rate.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.