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My textbook (Weste and Harris) asks the following:

Does the body effect of a process limit the number of transistors that can be placed in series in a CMOS gate at low frequencies?

It answers with the following:

No. Any number of transistors may be placed in series, although the delay increases with the square of the number of series transistors.

Now I'm not at a point where I've studied delay so I'll take that for granted, but why on Earth is the answer "No" in the first place? Consider, let's say, a PDN which is trying to discharge the capacitance on the output node of a custom CMOS logic gate. If I stack enough transistors in series, won't the high source voltages (and thus high threshold voltages) of the transistors "higher up"/closer to the high voltage output node utterly restrict (and perhaps completely cut off, neglecting subthreshold effects?) this discharge?

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  • \$\begingroup\$ As you start discharging the cap, the current will progressively reduce and hence the source voltages will also reduce. So, I do not understand your point. \$\endgroup\$
    – sai
    Commented Oct 17, 2023 at 16:58
  • \$\begingroup\$ What I am saying is that the source node voltages for the transistors which are "high up the stack" will be relatively high (much higher than ground, which is the source node voltage for the transistor at the bottom of the series stack). Thus, won't the transistors at the top of the stack cut off? @sai Indeed, my comment would seem to be true whether or not we consider the body effect; the body effect would just make it worse by also raising \$V_{th}\$ for the transistors with high source node voltages and thus cutting us off earlier. \$\endgroup\$
    – EE18
    Commented Oct 18, 2023 at 17:29
  • \$\begingroup\$ The sources being high will happen only if current is high. When you stack up a lot of NMOS transistors, the discharge current will start with a very low value such that the source voltages will be low enough to allow that small current without cutting off the path. \$\endgroup\$
    – sai
    Commented Oct 18, 2023 at 17:53
  • \$\begingroup\$ Are we making some assumptions about what the voltage on the various source nodes were before discharge here? @sai \$\endgroup\$
    – EE18
    Commented Oct 19, 2023 at 15:15
  • \$\begingroup\$ No, I am talking about during discharge. Just imagine, if source nodes go so high, current would cut-off as per your argument. If current is zero, how can the source nodes be so high? Isn't your argument contradictory? Source node voltages depend on the magnitude of current flowing. \$\endgroup\$
    – sai
    Commented Oct 19, 2023 at 17:03

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I think my problem was with not understanding what was meant by "limit" in the problem statement.

In terms of the setup of the problem, we are to imagine the setup for the problem as that we have a series stack PDN of NMOS transistors and that all transistors on the stack go from having 0 on their gates to 1 on their gates at the same instant, or that all were previously 1 except the bottom transistor which switches to 1 (and I guess based on leakage arguments or by assumption it would follow that these intermediate nodes are variously charged at some voltage between \$V_{DD}\$ down to \$GND\$) -- that is, basically the situation outlined in Figure 4.23 of the text:

enter image description here

I will call the NMOS nearest \$GND\$ as M1 and that nearest the output node as MN. It follows that the discharge begins with M1 and potentially some other Mi with source voltages not too high so that they can turn on as discharging, and that this propagates up the chain until eventually MN turns on. From this, it would seem to follow that the body effect \emph{does} matter, because it for a given source voltage on Mi, there will be less current draw from Mi because of the higher threshold voltage of Mi. This slows down the discharge of the PDN.

But by "limit" I think we mean "will the PDN eventually discharge completely", in which case I agree that the answer is "yes, and so the body effect has no difference." If this is the case, the allusion to "low frequencies" basically refers to low clock frequencies, so that we can "imagine the PDN has as much time as it needs to discharge".

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