My textbook (Weste and Harris) asks the following:
Does the body effect of a process limit the number of transistors that can be placed in series in a CMOS gate at low frequencies?
It answers with the following:
No. Any number of transistors may be placed in series, although the delay increases with the square of the number of series transistors.
Now I'm not at a point where I've studied delay so I'll take that for granted, but why on Earth is the answer "No" in the first place? Consider, let's say, a PDN which is trying to discharge the capacitance on the output node of a custom CMOS logic gate. If I stack enough transistors in series, won't the high source voltages (and thus high threshold voltages) of the transistors "higher up"/closer to the high voltage output node utterly restrict (and perhaps completely cut off, neglecting subthreshold effects?) this discharge?