Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

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22 views

FinFET Drain Resistance Values [closed]

I'm a recent graduate of Bachelors in Electronics & Instrumentation Engineering. Currently, working on a project involving transmission gate design using FinFETs. In college, we were told that the ...
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19 views

Is the minimum size of a poly contact in SCMOS 2x2 or 4x4?

By "SCMOS" I mean the "normal" MOSIS SCMOS rules, not SUBM or DEEP rules. All dimensions implicitly measured in lambdas. Also note that I have noticed that SCMOS rules are no longer as relevant as ...
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98 views

At what frequency does jumper wire stop functioning properly?

I have designed an IC with some digital circuitry requiring a 25 MHz clock signal. Now I'm designing a PCB to perform testing. My question is, would normal jumper wires be sufficient to pass a 25 MHz ...
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52 views

Logic Synthesizer generates bad timings

I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
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29 views

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit if NMOS and PMOS are interchanged?

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit, if the positions of \$NMOS\$ and \$PMOS\$ are interchanged?
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68 views

Is there any research for chemical/structural method to prevent observing beneath chip packaging? [closed]

I want to prevent others from reverse-engineering the on-die ROM, using X-ray, microscope, etc.. I think it's best to inject some substance between chip and packag and when the chip package is ...
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1answer
69 views

How to configure atmega 328 IO pins to reduce the power?

I am having a atmega328p for my home project. Consider the pins Pin B2 - connected to LDO enable. Output Pin D7 - MUX s0 Pin B0 - MUX s1 Pin B1 - MUX s2 Pin B4 - MUX s3 Pin c3 - MUX enable Pin B3 ...
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1answer
48 views

Threshold Voltage of OR Gate

What can be the possible DC and Transient analysis for OR gate using CMOS and the threshold voltage like we do for NAND or NOR? Or what can be the possible calculation to decide the W/L of PMOS and ...
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1answer
32 views

dynamic charge sharing between multiple gates

Based on this video: https://www.youtube.com/watch?v=CN4oIcAPIV4 hopefully it is legitimate I understand what is being done here. However, I don't understand it well enough for a more complex case ...
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22 views

Vlsi multi cycle path

In multi cycle path of 3 cycles, the setup for data D1 is checked at 3rd cycle. But for the next data, D2, the setup will be checked at 4th cycle or 6th cycle? I have this doubt because, data takes ...
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123 views

How to find un*Cox from Cadence Virtuoso?

Suppose we are posed with a problem statement saying to design a CS amplifier with specific gain. How do I design,or how do I get to know the value of gm,un,cox of the mos technology i am using. P.S: ...
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37 views

Are there MOS VLSI Process Design Kits (SPICE models) for free SPICE simulators?

I want to do some proof-of-concept work in IC analogue IC design. I know that plenty of free circuit simulators exist (LTSpce, NgSpice etc.), however they are meant for PCB simulation and most perform ...
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28 views

How to characterize a lower node transistor?

I am a fresh college graduate and have recently started working as analog design engineer. I am working on 22nm FDSOI technology, And characterizing this device has been trouble for me. The device is ...
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1answer
61 views

Transistors and Diodes maximum current per size

As you can understand my knowledge in electronics is limited. I am trying to find throughout the internet a way to find the maximum current I can put through a transistor or diode versus their size. ...
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1answer
36 views

Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
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3answers
98 views

Use condition from one clock with registers from another, synchronized clock

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency? This works as expected in simulation:...
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1answer
62 views

Is writing in FeRAM memory cell destructive?

I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
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3answers
129 views

Is there any memory cell that can store more than one bit? [closed]

SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
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99 views

Verilog code to drive a signal high always

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work. ...
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40 views

Find W/L and Vt of NMOS

I'm simply trying to find Vt and W/L for a given practice exam problem shown below: The solution is given as: Initially, I was trying to use the equation as shown in line 1 of the solution to ...
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37 views

How to write SDC for low frequency clocks?

I am working on a project involving a source clock with 1MHz frequency. Using a clock divider it is reduced to 4Hz. When I write SDC using the "create_generated_clock -divide_by" command I get an ...
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2answers
159 views

What tool produces this type of layout?

I don't under this layout figure (5.c) in pic attached. This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442 Alternate link for the ...
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86 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
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4answers
208 views

Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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1answer
103 views

Uncertainty(jitter) in setup and hold calculation

In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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1answer
40 views

Setup and hold in flipflops

Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge? The clock to capture flip flop is delayed ...
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30 views

What is propagation delay in cmos nets?

I have read somewhere that signal travels as electromagnetic waves in wires near to speed of light. The signals are brought to destination by EM waves. Then what does electrons do? If signals travel ...
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1answer
33 views

what triggers the PREADY signal in a slave of an APB?

I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state? If anyone could help me with this basic ...
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4answers
231 views

Why propagation delay is measured at 50% of the input and output waveform?

I didn't find the concept of propagation delay measured at a particular point on the waveform.
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69 views

Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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1answer
70 views

Why does the current in MOSFET have a quadratic function (explain logically without using the integration method)?

The current equation relating Vds ,Vgs and Vt is already known to us ,but if there is any way we can find out how it varies quadratically without using the formulae?
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51 views

Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use ...
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25 views

How conventional DFE (Decision Feedback Equalizer) works?

There are a lot of variations of DFEs online. But I couldn't find a step by step explanation on how for example the 2-tap DFE works. Can you provide an explanation with a scheme ? I looked for some ...
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1answer
101 views

Magic VLSI D flipflop with IRSIM

I'm working on a project in magic VLSI design tool and Ive been able to create a working D flip flop and simulated it correctly in the IRSIM. The end goal was to create a counter with D flip flops. ...
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51 views

Anneal Placement

I'm doing a practice assignment, and I cant seem to understand this question. They give 6 gates in a small 6x6 grid. Each gate is drawn as a circle with number. There are 4 nets, labeled A, B, C and ...
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1answer
276 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1answer
41 views

Why only shared resistances are taken into consideration while computing Elmore delay?

While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
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1answer
28 views

Understanding Transition faults

I learned that the transition faults model checks whether data transition meets the clock or not Transition Faults : Assumes large delay defect concentrated at one logical node, such that any ...
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4answers
4k views

Why aren't fully asynchronous circuits more prevalent? [closed]

From my understanding, most modern consumer CPU's are based on synchronous logic. Some high-speed applications (signal processing, etc.) use ansync logic for its higher speed. However, in today's ...
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1answer
279 views

Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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1answer
110 views

Why does writing to a read-only register increase current consumption?

Looking at the datasheet of the MSP430, it says writing to read-only registers results in increased current consumption. Why is that? What is happening when trying to write to a read-only section of ...
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1answer
135 views

Current to Voltage Converter in CMOS [closed]

If I want to use a 2-stage opamp for the current to voltage converter application, How should I check for the stability of the circuit? Will it need any kind of stability correction? An uncompensated ...
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2answers
166 views

Measuring maximum output current of Operational Amplifier

I just designed a two stage miller compensated operational amplifier, I am not sure how to measure it's maximum output current, Can you give me a precise definition of this current?
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2answers
230 views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
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2answers
218 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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1answer
80 views

How to know the size (W/L) for a circuit to source or sink a minimum of 4 times as much current as a minimum sized conventional inverter?

Consider the tri-state NAND below (i.e. if EN is high, output is NAND of A&B; if EN low, output is floating. Assume EN and ~EN always track). Show work. a) Label each transistor with a size which ...
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1answer
360 views

Machine learning for floorplanning

I have an educational assignment to make an floor-planning tool. Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
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1answer
124 views

Why does my AND cmos gate have less dissipation than my NAND gate?

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed : They both seem to be working ...
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1answer
43 views

Clock gating decreasing area

I read in the lecture slides to a VLSI course that clock gating also can lead to a decreased chip area size. In my understanding, clock gating decreases the chip size as this technique requires an ...
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1answer
177 views

VLSI channel routing: Why only route through channels?

I know that after placement you have your blocks and channels between the blocks. Now, the routing only takes place in the channels. My question is: Why can't we just route 'over' the blocks by ...

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