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Questions tagged [vlsi]

Stands for Very Large Scale Integrated circuits, which at one time had meaning in context to individual logic gates, and MSI (Medium Scale IC - UARTS etc.) with the advent of modern processes with Billions of transistors per design it is used as a generic term to mean IC's in common usage.

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28 views

Clock gating decreasing area

I read in the lecture slides to a VLSI course that clock gating also can lead to a decreased chip area size. In my understanding, clock gating decreases the chip size as this technique requires an ...
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1answer
40 views

VLSI channel routing: Why only route through channels?

I know that after placement you have your blocks and channels between the blocks. Now, the routing only takes place in the channels. My question is: Why can't we just route 'over' the blocks by ...
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93 views

Open-source layout routing tool [closed]

I am looking for an open-source circuit layout routing tool (with scripting option) for custom layout design. For example: I design a NAND schematic and convert it into layout and place components (...
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0answers
31 views

*WARNING* The directory: 'home/xslib/xslib' does not exist

I am working in cadence in VMWare virtual machine. Everything is working fine but some graph are showing unexpected. Also I am getting the warning, WARNING The directory: 'home/xslib/xslib' does ...
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11 views

How to select the nets from schematic in Test bench ADE cadence?

I'm performing my pre-layout simulation in cadence. I can select the output nets from test bench because I loaded the ADE environment for test bench but I also want to select the nets schematic as ...
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54 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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3answers
162 views

How to store the difference of 2 voltages on capacitor?

Suppose we have two voltages V1 and V2 how can we store the voltage difference (V1-V2) on a given capacitor? I tried charging the top plate of the capacitor to V1 ...
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24 views

SDIO protocol initialization commands [on hold]

I started working on SDIO protocol. In the initialization steps only I am getting struck at ACMD41 with argument 0x41060000. I got response CMD63 with argument 0x41ff8000. Afterwards host is sending ...
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1answer
43 views

CMOS Adder circuits

I have been studying VLSI Design and cannot seem to find the difference between the two adder circuits below. Both implement the functionality of a full adder with Generate, propagate and kill ...
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1answer
35 views

SvS for Verilog

which is the best possible way to perform Schematic vs Schematic for 2 Verilog gate-level codes? I want to do Svs just like people do for LvL in case of layout vs layout. SvS is also available for ...
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2answers
134 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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0answers
34 views

DIGITAL DESIGN - IRSIM 9.7: retrieve time of an event

I'm building an array multiplier (4x4, 8x8 and 16x16 versions) for a University Project in my Digital Design course. My dev tools are: Layout: Electric VLSI Functional Simulation: IRSIM 9.7 ...
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2answers
72 views

MOSFET Terminals in Layout

I am currently doing layouts in CMOS VLSI Design and I have gotten to drawing stick diagrams. The schematic of the 2 input NAND gate is shown below. In drawing the layouts I have trouble deciding ...
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1answer
197 views

Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
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2answers
73 views

Synthesising “constant” in VHDL

From point of view of a synthesiser, is there any difference between: Signal offset: std_logic_vector ( 3 downto 0) := "0100"; Constant offset: std_logic_vector ( 3 downto 0) := "0100";
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122 views

I'm learning to code a simple UART using verilog and code works only for RX purpose. There is something that i can't understand about the TX part?

I am trying to implement UART TX using three state FSM. The problem is that the received data is not transmitted serially, whenever "rd_en" is high.(No parity, only TX & RX) ...
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1answer
111 views

Why use more than one contact in VLSI layout?

I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer ...
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1answer
26 views

Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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1answer
115 views

question about wire load model [closed]

http://mantravlsi.blogspot.tw/2014/08/wire-load-model-wlm_1.html From the link, there is an instance of snapshot of a WLM.I can not figure out the number "1" in fanout_length("1",0.002) of the ...
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124 views

Digital Circuit Simulation Electric VLSI/LTSpice: .VEC command

I'm designing a series of arithmetic circuits for a Digital Design class. I must use Electric VLSI for layout and LTSpice from simulation. Since I'm builnd circuits with a lot of inputs (up to 64 for ...
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1answer
42 views

Which is the costliest step while designing BJT which makes it costlier against designing MOS? [closed]

Steps like oxidation, doping, epitaxy, photo-lithography, and metallization etc. are used in the designing process.
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1answer
87 views

How would you size the transistors in this problem?

I know that whenever you have series transistors multiply the equivalent W/L of the inverter by the number of series transistors. In the parallel case W/L remains the same. I don't know how to apply ...
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3answers
70 views

cannot figure what is the gate for this CMOS realization

i tried the to figure the what is this gate but i coud not it seems to pass one or high impedance on positive clock depending on the input and zero or high impedance on negative clock put i can't ...
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1answer
656 views

What is feedthrough in vlsi standard standard cell library gates?

I come across with the term feedthrough in standard library cells, but i did not understand its function.
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2answers
937 views

Floorplanning vs Placement in VLSI

The major steps of physical design that I learnt from a VLSI lecture are: 1)Partitioning 2)Floorplanning 3)Placement 4)Routing. The question of mine is about the steps 2 and 3. It seems like the ...
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2answers
108 views

Dynamic Voltage controlled Capacitor

I need a sinusoidal varying capacitor to test a differential capacitance circuit. I will use the circuit to test MEMS gyroscope/accelerometer capacitance change. But right now I do not have the ...
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1answer
321 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
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21 views

LVS shows following errors

i am new to cadence. When i ran the LVS i got this message. How to debug it?
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0answers
43 views

Use of a victim cache at L2 cache level in cache hierarchy

Is it advantageous to use a victim cache at the L2 or Last Level cache? I've seen references talking about victim cache implementation adjacent to direct mapped L1 caches. Would a level 2 victim ...
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0answers
81 views

Short circuit power dissipation for inverters (one with low Vt and other with regular Vt) with a common input

If 2 inverters are connected with common input, but one inverter is regular Vt (threshold voltage) and other is low Vt, which among the both will have more short circuit power dissipation? Since they ...
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1answer
2k views

Get_ports vs Get_pins vs Get_nets vs Get_registers

I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
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2answers
723 views

What is standard about standard cells in layout designing? [closed]

Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
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3answers
226 views

Design of 7400 Series IC

Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
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1answer
301 views

Calculating resistance for metal layer from LEF File

I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278. In the File description it is written as ...
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1answer
3k views

How to draw stick diagram of a function

I am a student of computer science and engineering. We have VLSI design in current semester. Now i am having trouble drawing stick diagram for a given equation. What is the step by step procedure for ...
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2answers
613 views

Why should the subthreshold swing value be small?

I am given to understand from the link below that a small value of subthreshold swing in MOSFETs implies that there is a better on-off current ratio. But, a small subthreshold swing would imply a ...
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5answers
1k views

CMOS logic Gates XOR

I'm currently doing the practice problems for CMOS VLSI Design 4th Edition. Question 1.6 says to use a combination of CMOS gates to generate the following functions (solution attached below function ...
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1answer
161 views

Why ring oscillator showing irregular graph ?

I'm trying to design ring oscillator in CADENCE using 180 CMOS .Instead of showing inverted clocking output , output changes in less then millivolt ranges. When I connect only 9 inverter like this ...
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2answers
387 views

Why VDDIO is more than VDDcore supply in VLSI/ integrated chips?

I have a question on different power supplies in a integrated circuit. I have seen VDDIO supply is more than VDDCore. If the input signal is more than the power signal, won't it affect the device?? ...
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1answer
422 views

What are advantages of 1's complement over 2's complement in DSP? [closed]

I wanted to know about the advantages of 1's complement over 2's complement in DSP applications.
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2answers
546 views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
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1answer
395 views

Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through

There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has ...
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1answer
170 views

Does this Verilog code infer a latch?

I wrote down these lines intentionally avoiding to reset the output o when rstb is asserted: ...
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1answer
63 views

Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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2answers
174 views

Clock Domain Crossing: Is it possible to design an architecture from faster to slower domain and slower to faster domain simultaneously?

If I have a design which has read clock and write clock, and I want to make it work for the following scenarios: faster read clock and slower write clock slower read clock and faster write clock Is ...
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1answer
332 views

How many stuck at faults are present in this circuit?

I was given a Verilog code of a circuit and was asked to find the number of stuck-at faults. The code was NOT INV1 (Y1, A); NOT INV2 (Y2, A); NOT INV3 (Y3, A); ...
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0answers
34 views

Multidimentional Variable Range Array in Systemverylog [duplicate]

Please anyone tell me how to declare multidimentional variable range array in systemverylog. i.e I need to declare 2D array of size 'm' rows and 'n' columns. logic v[m-1:0][n-1:0]; giving me an error ...
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0answers
93 views

What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?

Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
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1answer
85 views

What triggered the need for VLSI chips in modems post 1200 baud?

I was chatting to my boss today and he said: My first job was electrical working in a factory for a modem company. The last model modem we made was the 1200 baud. After that they needed ...
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1answer
78 views

What could be a good project to realize neural network in hardware (VLSI) for a beginner? [closed]

As a beginner how can I start implementing neural network using CMOS technology. I have come across implementing neural nets that mimic basic gates.