Questions tagged [vlsi]

VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.

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On DC transfer characteristics, logic levels, and the static discipline

One thing that's confused me ever since I started studying digital design is what it means when books say, roughly, that we can choose or define the input and output thresholds for a given circuit ...
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Issue in understanding routing in VLSI CAD

I have chosen to undertake VLSI CAD as a part of my electronics degree and I came across this statement (Source : Naveed Sherwani, Algorithms for VLSI Physical Design Automation, 3rd edition , Chapter ...
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?

In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
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Understanding the rigorous definition of hold time

Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition. Now I am familiar with the common/heuristic ...
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Why do I need multiple segments to model the RC flight time of interconnect?

Consider a problem where we are interested in computing the delay for a signal to propagate to some load capacitance after a step input on the driving logic gate, and let there be a nonnegligible ...
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Does minimizing stages necessarily give best outcome when designing circuit under a delay constraint?

In the context of digital design, a common situation is to have to design a circuit for minimum energy under a delay constraint. Suppose a given circuit can be implemented with various stages. Is it ...
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Why do we need output isolation for power-gated blocks?

In their CMOS VLSI Design, Weste and Harris give the following discussion of power gating a block of logic: I am in particular interested in understanding the need for output isolation here. Is the ...
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Calculate Acitivity Factor in VLSI

Here is the problem: And this is my solution: activity factor = probility output node is 1 x (1 - probility output node is 1) Source: E., W.N.H. and Harris, D.M. (2011) CMOS VLSI Design: A circuits ...
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On different well processes (fabrication process)

My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the nature of fabricating wells in the twin-well and triple-well processes. My question here is about how we can use so few ...
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On different well processes (reasons)

My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the difference between n-well, twin-well, and triple-well processes. My question here is about the reasons why we want to &...
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Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in saturation?

A relevant figure of merit for a CMOS inverter is the so-called input threshold voltage (no relationship to the threshold voltage of a given MOSFET) \$V_{inv}\$, defined as the voltage \$V_{in}\$ at ...
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Justification for equivalent gate capacitance simplification in digital circuits

A MOSFET is, in reality, a four-terminal device with capacitances between each pair of terminals: These capacitances are, of course, the standard MOSFET intrinsic and extrinsic differential ...
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What does optimizing fabs "for throughput rather than latency" mean?

In the context of a whirlwind tour of the modern VLSI design, tapeout, and fabrication flow in their CMOS VLSI Design, Weste and Harris write the following: Multiple chips are manufactured ...
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Why do we alternate directions between metal layers?

In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that Another important decision during floorplanning is ...
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Why do two nonoverlapping phase completely obviate the possibility of hold time issues?

In Weste and Harris's CMOS VLSI Design, they write In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop ...
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When working with a technology node (say 14nm), should I keep the gate lengths of the FETs strictly equal to the minimum gate length?

When doing simulations with a technology node, say 14nm, can I change the gate lengths of FETs as per my wish? If I need a FET with 140nm gate length, should I set the gate length of the transistor ...
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What does ‘full custom’ really mean?

It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
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On understanding tradeoffs associated with pipeline depth

In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the ...
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How does MOSIS let designers “share” a mask set?

In Weste and Harris's CMOS VLSI Design, they describe MOSIS as follows: The MOSIS service [Piña02] is a low-cost prototyping service that collects designs from academic, commercial, and government ...
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Why do we use a MUX rather than tristate buffers to implement a bus?

Consider a small digital system consisting of registers connected to a bus interconnection network. It is well-known that the output to the bus can (functionally) be implemented either with tristate ...
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Is there any problem with implementing a tristate buffer this way?

Consider the following implementation of an inverting tristate buffer in CMOS: My textbook (Weste and Harris's CMOS VLSI Design) says that to implement a (noninverting) tristate buffer we should ...
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How does this logic gate naming convention work?

In their CMOS VLSI Design, Weste and Harris seem to use a naming convention for logic gates which I cannot quite seem to define in my head. Ill give the two examples they use and hopefully someone ...
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Why does the body effect result in these \$V_{OH}\$ and \$V_{OL}\$ values?

Consider the following circuit and discussion which come from my textbook (Brown and Varnesic Fundamentals of Digital Logic): Of course, the exercise is to notice that NMOS and PMOS are very bad in a ...
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What is the difference between a tristate buffer and a transmission gate?

Functionally, these two "blocks" seem to do the same thing: send input to output if enabled and present high impedance Z on the output if not. However, this answer seems to suggest a ...
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What is PDN in these questions?

I don't know what PDN stands for. Can you give me some hint to solve these problem. I'm appreciate.
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Capacitances for inverter delay calculations

In CMOS VLSI DESIGN, Neil WESTE, page 144. "The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. It ...
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What is wrong with this XOR gate layout?

I am learning how to make layout for various CMOS gates in MAGIC. I tried to make layout for a 2 input XOR gate in MAGIC. To the best of my knowledge it should work fine when extracted to SPICE. But ...
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Why doesn't voltage on one terminal of a capacitor matter?

In the context of characterizing the load driven by an inverter by an effective capacitance, my textbook (CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, by Weste and Harris) gives ...
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Why doesn't body effect place limit on number of series transistors in CMOS network?

My textbook (Weste and Harris) asks the following: Does the body effect of a process limit the number of transistors that can be placed in series in a CMOS gate at low frequencies? It answers with ...
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Why is length scaling equivalent to series transistors?

In what follows, I am neglecting all non-idealities. All transistors are assumed to obey the first-order, long-channel IV characteristics. My VLSI text (Weste and Harris) claims that, given these ...
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Why do series NMOS do better than a single NMOS from a delay perspective?

My VLSI text (Weste and Harris) writes the following: Transistors in series drop part of the voltage across each transistor and thus experience smaller fields and less velocity saturation than single ...
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Why does Backside Power Distribution work for high speed CPUs?

Several upcoming or future CMOS process nodes are said to offer some kind of backside power delivery for Silicon CMOS transistors, so the precious area in the lower metal layers is freed up for signal ...
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Pin inductance vs pin capacitance in determining rise and fall times

I am a beginner in digital electronics and VLSI. I know that pin capacitance is an important parameter in determining the rise and fall times of logic gates and ICs. This is supported by my intuition ...
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What is the purpose of design rules in VLSI

My doubt is what does it means micron and lamba design rules? And does it have any connections with nanometer process (eg. 7nm,14nm on microprocessor). Actually what is the purpose of these design ...
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Which type of mosfet used to make CMOS inverter?

My doubt is which type of mosfet used to make CMOS inverter Enhancement or depletion ?
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How is the propagation delay of a CMOS inverter proportional to the time constant of the output capacitance? [duplicate]

I was reading a book on VLSI design and came across a chapter explaining the working of a CMOS inverter. A part of the chapter describes how the time it takes to switch between high to low or low to ...
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What is the propagation delay of a carry save adder?

I was reading this paper about the Comparison of Adder Topologies, when I came across a page talking about the Carry Save Adder. They say on page 3: The propagation delay is 3 gates regardless of the ...
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What determines the maximum clock rate for a CPU?

What factors determine the maximum CPU clock rate? A 6502, for instance, clocks in the megahertz range, while an Intel x64 chip typically clocks in the gigahertz range. All things being equal, if the ...
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Why do we use LDD technique in IC fabrication technology?

Why do we use LDD(lightly doped drain) in IC fabrication technology? In the "silicon VLSI technology" book, was mentioned that this is in order to create a voltage drop in drain region. So ...
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Using a latch vs an AND gate to reduce switching activity in a low power VLSI design

Here is a problem that pops in low power design interview questions. The solution is the second picture down. Why not use AND gates in place of the D-Latch? The person who created the solution did not ...
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How do I get more clarity on the meaning of "integration" in VLSI?

VLSI and advances in our understanding of semiconductor physics has made it possible to have enormous computing capacity at our fingertips. However, I never really understood what "integration&...
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Pin vs Port terminology in SDC

In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
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Why is the gamma term missing in the first case of single transistor example?

This is the video. How is the gamma term present in one case and absent in another?
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Will the saturation current through one of these NMOS circuits always be greater than the other?

Is there a definitive way to know for all cases if an NMOS would have a greater saturation current if a resistor R is connected to 1) the drain side or 2) the source side? The assumption is that the ...
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I·R drop challenges in advanced node design [closed]

If I·R (current-resistance) drop affects the power grid of a VLSI mixed signal chip on advanced nodes below 7 nm, then why don't we just bump up the voltage to compensate for the loss in I·R drop? For ...
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What are horizontal and vertical track pitches?

I was experimenting on OpenLANE with Sky130 PDK and below is the tracks.info file. I learned from a workshop that the values pertain to the track pitches as ...
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Calculating CMOS threshold voltage

I found this solution in a textbook, and I do not understand how they calculated Vth2 (typo written as 'Vth' at the bottom). More specifically, where does the 2Vm come from? I understand that Ids1 = ...
RGB Engineer's user avatar
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Measuring the number of pulses and updating the counter after a certain number of pulses have occured using Verilog

I am trying to build a counter using Verilog which will update itself after a certain number of pulses have been detected. For example, if I am giving a 10kHz input, after every 10 pulses have been ...
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Can we calculate leakage power after synthesis at the architectural level power analysis itself?

As I understand it, leakage power depends after implementation and not on the architectural level itself. When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
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How does an aggressor raise/drop the voltage of the victim in crosstalk?

I have been trying to understand, intuitively and physically, how crosstalk works. If I have a net that is switching (from either LO to HI or from HI to LO) running adjacent to a static line (LO or HI)...
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