Questions tagged [vlsi]

VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.

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how can i design 4 bit division circuit using best approach based on vlsi design techniques? [closed]

I need to design a general 4 bit division circuit using the best approach considering minimum number of transistors but unable to construct it.
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How to make diodes and bonding pads in Electric (ID design program)?

I'm a beginner user of Electric, a free VLSI/IC design program. Let me preface, that the last time I've used an IC design program was nine years ago at University. We used Cadence Virtuoso back then. ...
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Capture register value at specific instance in Verilog

I created two always blocks in Verilog. In one always block, one bit register variable is flipping and in other always block, a counter variable is running. Now when counter will reach to a specific ...
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157 views

What is the triangle symbol in circuit diagrams?

What is the triagular symbols shown in the image, is it a buffer or some kind of delay?
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Why Tcd and Tpd is different in combinational ckt?

In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons: Different rising and falling delays, ...
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what does qualcomm MDM6085 do?

This is my first question in this stack exchange. I found my old Reliance Netconnect+ modem and decided to open it up. There is a micro chip with the name QUALCOMM MDM6085 on the top left and EAB857.0 ...
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81 views

Calculating propagation delay for a logic circuit

Given the above combinational logic diagram, How to calculate the propagation delay? AND->OR->AND-NOT NOT->AND->NOT I see the above two longest paths. So what I understand is just take ...
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Why can't conductors be used in making ICs (integrated circuits) instead of semiconductors? [closed]

I really wanted to ask why we can not control flow of electrons in conductors. Can I not say if a current is flowing in a conductor it is 1 and when I disconnect the supply it is 0. Can you elaborate ...
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IV characteristics of NMOS transitor

I have used the model of the GPDK90 transitor in Cadence. I have few questions regarding the IV characteristics: Why does the threshold voltage change with change with Vds (Vds= 0, 1.25, 2.5, 3.75 ...
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Barrel shifter in verilog

I am new to verilog . I have instantiated a 4-bit barrel shifter in my top module design. shift_mag is the amount by which i am shifting the input. ...
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How do ASIC designers approach designing for extremely low supply voltages like 0.3V?

In ASIC design, there is a tradeoff between performance and energy efficiency. Since most consumer CPU's are designed for maximum performance, they operate at high voltages and clock frequencies, ...
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Why does Moore Finite State Machine need more states than Mealy Finite State Machine?

I was reading about finite state machines. I read about Moore and Mealy machine and also the state representation. I read that in the Moore machine the output depends on the present state only and in ...
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86 views

Drawing a 2:1 CMOS inverter

What is meant by "draw a 2:1 CMOS inverter with lambda design rules?" Do I have to take double scale while drawing PMos in the layout diagram?
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How to find what circuitry is required for synthesis of following digital VLSI design problem?

My thoughts: Here price of chocolate is increasing in Geometric progression with common ratio 2 and first term 1, so on nth day price of chocolate will be $T_{n}=2^{n-1}$\ irrespective of wheather ...
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50 views

Systemverilog interface definition - lint error message

I'm using Systemverilog interfaces to enable the implementation of generic functions. The interface is defined in one file as follows: ...
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Path exceptions modeling for ETM

On page 3 of Hierarchical Timing Analysis: Pros, Cons,and a New Approach , how is set_output_delay related to set_multicycle_path here in this case ? and how to re-code the path exceptions ? Any ...
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210 views

Why does decreasing the voltage also decrease the circuit frequency?

In CMOS circuit design, we know dynamic power is propotional to \$V_{dd}^2Cf\$, so the best way to reduce dynamic power is to reduce Vdd. However, according to the textbook, Keeping the same clock ...
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67 views

Needed help in drawing CMOS design and euler path p-tree ,n-tree for boolean function

I have the expression \$Z=(A(D+E)+(BC))'\$, I'm trying to draw CMOS logic but I guess I've gone wrong somewhere. I'm unable to draw Euler path for this diagram
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
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what is the specific reason for using FIFO in asynchronous domain at VLSI?

I was wondering that the reason of using FIFO in asynchronous domain at VLSI. Basically, to prevent x propagation in asynchronous domain(aka CDC domain), I was taken care of 2 stage F/F method for ...
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Why do we declare the inputs of our design as reg in testbench and outputs as wire?

Why do we declare the inputs of our design as reg in testbench and outputs as wire?
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47 views

Load Capacitance in CMOS Circuits

I am studying VLSI Coursers and I came up to a question. what happens if we don't use output load in CMOS circuits? what happens to overshoot/undershoot and circuit delay? thanks
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45 views

General CMOS circuit

In any CMOS circuit like an inverter or an n-input NOR or NAND gate, where the pMOS network is connected at the top to Vdd source terminal and nMOS network is connected at the bottom to the ground ...
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Calling a function that's defined in an interface

I defined an interface and a function inside it as follows: ...
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101 views

What is the origin of the “iso [frequency/voltage/power]” terminology?

In the VLSI and computer architecture world, it is common to hear terms like "iso frequency" or "iso power" when comparing the performance of different designs. My understanding is ...
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116 views

Errors in VHDL code

The VHDL code was written by me for a 4-bit PIPO DFF register. I have been encountering some errors when i did so. Kindly check the code and errors below. ...
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I need to write a verilog code to generate a signal which goes high for one clock pulse after every tenth clock pulse

I need to write verilog code wherein I need a signal which goes high for one clock pulse after every tenth clock pulse. I tried something this way, ...
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Why would an AND gate need six transistors?

I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense ...
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What causes these peaks in the output voltage of a CMOS inverter?

The figure is taken from https://ece.uwaterloo.ca/~mhanis/ece637/lecture7.pdf There is no significant inductive element in a CMOS inverter, so what is the cause of these peaks while switching?
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Confusion about time borrowing

After studying timing analyzing in FPGA I still have some confusions about time borrowing like the following: I have seen some of this site EE having good reputation saying that time borrowing is ...
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Location transformation of parasitics

I have an question for which I could not get an answer, even from google. What is location transformation for parasitic? How do people deal with it? And what is the significance of it in whole vlsi ...
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140 views

Demo of designing a modern CPU in Verilog/VHDL [closed]

Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/...
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95 views

Efficient single cycle huffman decoding technique with wider input data?

I have a wider input data (Byte width) running in my system, and I'm implementing a huffman decoding on this incoming data. Since, the Huffman encoded words don't have the fixed length, hence I need ...
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85 views

Is state machine based sequence detector easier to verify than shift register based one?

Suppose I have two versions of sequence detectors: one is based on let's say Moore machine and the other one is based on simple shift register & comparator. Which one among these is easy to verify ...
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Logical Effort in complex circuit - Output capacitance

As part of a VLSI course I was asked to estimate the delay of an ALU, similar to the one described in the picture, using Logical Effort method. I calculated the delay of the critical path through the ...
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Consider lowering VDD to save power in a static CMOS gate. Also scale Vt proportionally to maintain performance

Will the dynamic power consumption go up or down? Will the static power consumption go up or down? Explain with proper analytics. I came accross this question while solving a question booklet issued ...
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166 views

Whose power reduction is better. Clock gating or Data enable?

I am comparing Clock Gating (ECG) and Data enable methods in term of power reduction. Both can save power. But which one is better? I tried these 2 methods in a small design ( a d flipflop ) to a ...
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118 views

12-bit pipelined adder

I have been given the task of designing a 12-bit pipelined adder: There are 4-bit adders connected by latches. Why are latches used between the 4-bit adders? Is it for synchronization?
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How can we validate the MCP (multi cycle) settings in SDC if the design is huge?

Is there any standard method or tool available for validation of the multi cycle paths that are set as part of the SDC file during timing analysis. For small designs manual validation can be performed ...
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Why are photomasks so expensive?

I just read the answer to this question asking how much a custom ASIC costs. It says that When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (...
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SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...
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61 views

What is the difference between operating temperature and junction temperature of an IC?

On Wikipedia, I found that these are the same. However, in datasheets I find two different temperature ranges. Can somone explain the difference to me please?
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111 views

How is a PMOS transistor used as a switch?

I am trying to understand switching behaviour of PMOS transistor and how exactly it passes a bad 0 value. I'm getting confused with the notation. More specifically, when the PMOS is on and $$V_(in)=...
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I am trying to instantiate few modules to work in top level design, but even though there is no error but I am not getting proper output

This is my verilog code. Though I am not getting any output, if any two of the instantiated modules are commented then I am getting proper partial output(For full output I need all of them to work). ...
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Zero in a basic RC high pass filter

If I write the transfer function I can clearly see a zero at zero frequency and a pole at 1/2πRC frequency. But If I simply look at this circuit I would say that there is one pole and no zero(as there ...
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How do the VLSI design rules for finFET differ from traditional MOSFET/CMOS design?

I'm taking an intro to VLSI class right now and we're learning the design rules for laying out chips on a 600 nm process. This was the state of the art in the early 90's so it should be a little out ...
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47 views

What exactly do the well taps in MOSFETs do and how?

Do they affect the flow of charge carriers or charge concentrations at all in the device? How so? Up to this point I've tried to visualize the effects that the various doped areas had on device ...
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How do I approximate number of calculations/operations/memory/hardware is required for a 2^18 point FFT on chip?

I am looking for FFT implementation on Chip/FPGA. I need a high-resolution FFT which is a minimum of 2^18 points. However, I need to approximate how much hardware will I require for this process. I ...
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Application of set_clock_latency

I am learning about VLSI static timing analysis (STA) and some applications of SDC commands. I'm probably still missing some big picture concepts, but my question is about "why" when it comes to using ...
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44 views

CADENCE wireless connection

I would like to know if you have a way to call without needing a line of communication at CADENCE? See the example in the PROTEUS software image, at the time I made the connections without needing ...

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