Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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What are the "rules" for counting transistors on a chip?
It seems straightforward to count the transistors on a chip, but it's not.
For instance, many logic gates use transistors in parallel to increase the drive current. Are these transistors counted as ...
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What would the critical path be for this circuit? [closed]
I have the following circuit for which I need the critical path:
For Path 1:
This has the maximum number of stages
Logical effort (NAND3) = 5/3. Total parasitic effort for this stage (excluding ...
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Why does this LC VCO work without varactor but becomes really noisy as soon as I add the varactors?
I am trying to design an LC VCO in TSMC's 65nm CMOS process. First I designed an LC oscillator without any tuning i.e. I used MIM capacitors which are included with the PDK as well as inductors from ...
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How to decide sizes for transistors in a design? What does it mean to design an IC?
I have recently started designing analog ICs as part of my academic work. So far all I do is take topologies given in textbooks or papers and try to design them in the PDKs available at my university. ...
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FD-SOI Channel formation with fully depleted body
In an FD-SOI the body is undoped, which could be just an intrinsic semiconductor such as silicon. What I'm wondering is how the channel is formed in an FD-SOI when the body isn't doped at all. My ...
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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Clock feedthrough of the bootstrapped switch
I'm learning about the bootstrapped switch through this paper. Razavi used a 20 µm / 28 nm NMOS (M1) as the main switch to achieve low Ron. I am wondering does this wide device cause any problem ...
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How does analog IC benefit from channel length shrinking?
I have some experience in OTA design for both 180 nm and 130 nm technologies. I didn't see much advantage of using 130 nm, as I had to use quite long channel length to achieve an acceptable gain in ...
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How to implement 2 stage pre-decoding
I've been studying VLSI and I came across a design problem regarding decoders.
Let's same I want to design a 12:4096 decoder using inverters, NAND 3 and NOR4 gates. Implementing this decoder without ...
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can someone explain the working /operation of FinFET?
Any resources that give in depth analysis of FinFET working would be helpful.
I read a couple of papers on IEEE but most of them had very little information related to the working principle.
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Transistors sizing on commercial VLSI custom design projects
I have a doubt regarding the way circuits sizing is carried out in custom design style commercial projects.
For example, let consider the design of a fast adder for a high performance CPU.
At logical ...
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Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?
I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters.
This is the information of the NMOS circuit to be designed.
Using transistor model level 1 parameters, ...
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In vlsi physical design ,what are the concepts to check for high standard cell growth?
What are the different checks that are usually done when there is a high standard cell growth from one stage to the next.
Eg: from place to CTS of there is a high standard cell growth what could be ...
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A question about layout: How to connect the gate to metal 1 layer?
I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer)
In the process I used, there's a design rule ...
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What is the standard procedure for analogue IC tapeout?
This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
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Why are interrupts active low? [closed]
Came across this question recently and saw some answers too, but need a simple answer which is easy to understand.
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On DC transfer characteristics, logic levels, and the static discipline
One thing that's confused me ever since I started studying digital design is what it means when books say, roughly, that we can choose or define the input and output thresholds for a given circuit ...
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Issue in understanding routing in VLSI CAD
I have chosen to undertake VLSI CAD as a part of my electronics degree and I came across this statement (Source : Naveed Sherwani, Algorithms for VLSI Physical Design Automation, 3rd edition , Chapter ...
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
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Understanding the rigorous definition of hold time
Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition.
Now I am familiar with the common/heuristic ...
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Why do I need multiple segments to model the RC flight time of interconnect?
Consider a problem where we are interested in computing the delay for a signal to propagate to some load capacitance after a step input on the driving logic gate, and let there be a nonnegligible ...
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Does minimizing stages necessarily give best outcome when designing circuit under a delay constraint?
In the context of digital design, a common situation is to have to design a circuit for minimum energy under a delay constraint. Suppose a given circuit can be implemented with various stages. Is it ...
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Why do we need output isolation for power-gated blocks?
In their CMOS VLSI Design, Weste and Harris give the following discussion of power gating a block of logic:
I am in particular interested in understanding the need for output isolation here. Is the ...
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Calculate Acitivity Factor in VLSI
Here is the problem:
And this is my solution: activity factor = probility output node is 1 x (1 - probility output node is 1)
Source: E., W.N.H. and Harris, D.M. (2011) CMOS VLSI Design: A circuits ...
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On different well processes (fabrication process)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the nature of fabricating wells in the twin-well and triple-well processes. My question here is about how we can use so few ...
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On different well processes (reasons)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the difference between n-well, twin-well, and triple-well processes. My question here is about the reasons why we want to &...
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Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in saturation?
A relevant figure of merit for a CMOS inverter is the so-called input threshold voltage (no relationship to the threshold voltage of a given MOSFET) \$V_{inv}\$, defined as the voltage \$V_{in}\$ at ...
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Justification for equivalent gate capacitance simplification in digital circuits
A MOSFET is, in reality, a four-terminal device with capacitances between each pair of terminals:
These capacitances are, of course, the standard MOSFET intrinsic and extrinsic differential ...
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What does optimizing fabs "for throughput rather than latency" mean?
In the context of a whirlwind tour of the modern VLSI design, tapeout, and fabrication flow in their CMOS VLSI Design, Weste and Harris write the following:
Multiple chips are manufactured ...
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Why do we alternate directions between metal layers?
In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that
Another important decision during floorplanning is ...
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Why do two nonoverlapping phase completely obviate the possibility of hold time issues?
In Weste and Harris's CMOS VLSI Design, they write
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop ...
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When working with a technology node (say 14nm), should I keep the gate lengths of the FETs strictly equal to the minimum gate length?
When doing simulations with a technology node, say 14nm, can I change the gate lengths of FETs as per my wish?
If I need a FET with 140nm gate length, should I set the gate length of the transistor ...
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What does ‘full custom’ really mean?
It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
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On understanding tradeoffs associated with pipeline depth
In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the ...
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How does MOSIS let designers “share” a mask set?
In Weste and Harris's CMOS VLSI Design, they describe MOSIS as follows:
The MOSIS service [Piña02] is a low-cost prototyping service that collects designs from academic, commercial, and government ...
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Why do we use a MUX rather than tristate buffers to implement a bus?
Consider a small digital system consisting of registers connected to a bus interconnection network. It is well-known that the output to the bus can (functionally) be implemented either with tristate ...
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Is there any problem with implementing a tristate buffer this way?
Consider the following implementation of an inverting tristate buffer in CMOS:
My textbook (Weste and Harris's CMOS VLSI Design) says that to implement a (noninverting) tristate buffer we should ...
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How does this logic gate naming convention work?
In their CMOS VLSI Design, Weste and Harris seem to use a naming convention for logic gates which I cannot quite seem to define in my head. Ill give the two examples they use and hopefully someone ...
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Why does the body effect result in these \$V_{OH}\$ and \$V_{OL}\$ values?
Consider the following circuit and discussion which come from my textbook (Brown and Varnesic Fundamentals of Digital Logic):
Of course, the exercise is to notice that NMOS and PMOS are very bad in a ...
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What is the difference between a tristate buffer and a transmission gate?
Functionally, these two "blocks" seem to do the same thing: send input to output if enabled and present high impedance Z on the output if not. However, this answer seems to suggest a ...
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What is PDN in these questions?
I don't know what PDN stands for.
Can you give me some hint to solve these problem. I'm appreciate.
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Capacitances for inverter delay calculations
In CMOS VLSI DESIGN, Neil WESTE, page 144.
"The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. It ...
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What is wrong with this XOR gate layout?
I am learning how to make layout for various CMOS gates in MAGIC. I tried to make layout for a 2 input XOR gate in MAGIC. To the best of my knowledge it should work fine when extracted to SPICE. But ...
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Why doesn't voltage on one terminal of a capacitor matter?
In the context of characterizing the load driven by an inverter by an effective capacitance, my textbook (CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, by Weste and Harris) gives ...
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Why doesn't body effect place limit on number of series transistors in CMOS network?
My textbook (Weste and Harris) asks the following:
Does the body effect of a process limit the number of transistors that can be placed in series in a CMOS gate at low frequencies?
It answers with ...
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Why is length scaling equivalent to series transistors?
In what follows, I am neglecting all non-idealities. All transistors are assumed to obey the first-order, long-channel IV characteristics.
My VLSI text (Weste and Harris) claims that, given these ...
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Why do series NMOS do better than a single NMOS from a delay perspective?
My VLSI text (Weste and Harris) writes the following:
Transistors in series drop part of the voltage across each transistor and thus experience smaller fields and less velocity saturation than single ...
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Why does Backside Power Distribution work for high speed CPUs?
Several upcoming or future CMOS process nodes are said to offer some kind of backside power delivery for Silicon CMOS transistors, so the precious area in the lower metal layers is freed up for signal ...
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Pin inductance vs pin capacitance in determining rise and fall times
I am a beginner in digital electronics and VLSI.
I know that pin capacitance is an important parameter in determining the rise and fall times of logic gates and ICs.
This is supported by my intuition ...
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What is the purpose of design rules in VLSI
My doubt is what does it means micron and lamba design rules? And does it have any connections with nanometer process (eg. 7nm,14nm on microprocessor).
Actually what is the purpose of these design ...
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