Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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How to solve circuits with charged capacitor?
I have to solve following two questions. Now I have figured two methods to solve them. For Question 1, both methods are giving me same results but for Question 2 the results are different.
I am facing ...
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What is the purpose of design rules in VLSI
My doubt is what does it means micron and lamba design rules? And does it have any connections with nanometer process (eg. 7nm,14nm on microprocessor).
Actually what is the purpose of these design ...
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Which type of mosfet used to make CMOS inverter?
My doubt is which type of mosfet used to make CMOS inverter Enhancement or depletion ?
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How is the propagation delay of a CMOS inverter proportional to the time constant of the output capacitance? [duplicate]
I was reading a book on VLSI design and came across a chapter explaining the working of a CMOS inverter. A part of the chapter describes how the time it takes to switch between high to low or low to ...
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What is the propagation delay of a carry save adder?
I was reading this paper about the Comparison of Adder Topologies, when I came across a page talking about the Carry Save Adder. They say on page 3:
The propagation delay is 3 gates regardless of the ...
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What determines the maximum clock rate for a CPU?
What factors determine the maximum CPU clock rate? A 6502, for instance, clocks in the megahertz range, while an Intel x64 chip typically clocks in the gigahertz range.
All things being equal, if the ...
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Why do we use LDD technique in IC fabrication technology?
Why do we use LDD(lightly doped drain) in IC fabrication technology?
In the "silicon VLSI technology" book, was mentioned that this is in order to create a voltage drop in drain region. So ...
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Using a latch vs an AND gate to reduce switching activity in a low power VLSI design
Here is a problem that pops in low power design interview questions. The solution is the second picture down.
Why not use AND gates in place of the D-Latch? The person who created the solution did not ...
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How do I get more clarity on the meaning of "integration" in VLSI?
VLSI and advances in our understanding of semiconductor physics has made it possible to have enormous computing capacity at our fingertips.
However, I never really understood what "integration&...
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Pin vs Port terminology in SDC
In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
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Why is the gamma term missing in the first case of single transistor example?
This is the video.
How is the gamma term present in one case and absent in another?
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Will the saturation current through one of these NMOS circuits always be greater than the other?
Is there a definitive way to know for all cases if an NMOS would have a greater saturation current if a resistor R is connected to 1) the drain side or 2) the source side?
The assumption is that the ...
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I·R drop challenges in advanced node design [closed]
If I·R (current-resistance) drop affects the power grid of a VLSI mixed signal chip on advanced nodes below 7 nm, then why don't we just bump up the voltage to compensate for the loss in I·R drop?
For ...
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What are horizontal and vertical track pitches?
I was experimenting on OpenLANE with Sky130 PDK and below is the tracks.info file. I learned from a workshop that the values pertain to the track pitches as ...
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Calculating CMOS threshold voltage
I found this solution in a textbook, and I do not understand how they calculated Vth2 (typo written as 'Vth' at the bottom).
More specifically, where does the 2Vm come from?
I understand that Ids1 = ...
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Measuring the number of pulses and updating the counter after a certain number of pulses have occured using Verilog
I am trying to build a counter using Verilog which will update itself after a certain number of pulses have been detected. For example, if I am giving a 10kHz input, after every 10 pulses have been ...
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Can we calculate leakage power after synthesis at the architectural level power analysis itself?
As I understand it, leakage power depends after implementation and not on the architectural level itself.
When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
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How does an aggressor raise/drop the voltage of the victim in crosstalk?
I have been trying to understand, intuitively and physically, how crosstalk works. If I have a net that is switching (from either LO to HI or from HI to LO) running adjacent to a static line (LO or HI)...
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Why AND-Latch based clock gate (ICG cell) is not reliable only when driving negative edge triggered FFs?
I'm reading the paper "A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability"
https://ieeexplore.ieee.org/document/8702507
It says that with AND-Latch based ICG there could ...
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CPU Dynamic voltage frequency scaling - does reducing both frequency and voltage always imply reduction in current?
Referring to the equation for dynamic power P=C·V2·f, is it always assumed that reducing voltage and frequency means a reduction in power and therefore current?
Example: let's assume for this argument ...
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RHP pole of two stage OTA
I learnt that for any amplifier (with some capacitor) if we short/open the capacitor and the polarity of gain changes, it is a sign of RHP zero.
Now, while applying the same analysis I obsevred that ...
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Why use transistors at all for building gates? Alternatively: what about sub-transistor level optimization?
I was thinking about transistor design, and how the classic AND gate is composed of two transistors in series. See this image:
Now if we look at how a transistor itself is designed we can expand the ...
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How to automatically add signals in GTKwave when opened?
I use GHDL and GTKwave to compile/simulate and see the waveform of my VHDL code. Is there any way to automatically append signals in GTKwave's signals window when opened?
The problem is that I ...
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Op-amp output error due to non-infinite open-loop gain [duplicate]
Before asking the question I would like to attach the image of the BGR regarding which I have some doubts:
From what I have read, due to the high gain of the op-amp, the two inputs of the op-amp, Va ...
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How can I design a digital circuit where the output is 5 times the input? [closed]
I tried to solve this challenge by enhancing my skills in digital circuits, but could not solve it.
How can I design a digital circuit where the input is only 2 bits and the output equals 5 times the ...
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Slew rate of two stage OTA
I have learnt two stage opamp designing from books and yourtube videos, but have always failed to understand slew rate formula which is I5/Cc(I5 is bias current of M5 and Cc is compensation capacitor)....
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RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?
Given the below scenario, which is a reset-domain-crossing violation :
Can it be resolved using some reset synchronization strategy?
Is such design considered bad to begin with, i.e. need to avoid ...
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What can procedural statements do that assignment statements cannot do in Verilog?
It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does ...
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MOSFET gate area?
I have a transistor with constant Vdd voltage but my W, L parameters are decreasing - what happens to my gate area?
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Processor Design: Just how complex is a real CPU datapath?
We're doing a course on Computer Architecture, and the course project involves creating an ARM-based processor.
We're supposed to create the processor in stages, and add significant features in each ...
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Is it possible to design dynamic logic using pre-discharge NMOS transistor and evaluation done using PMOS?
Traditionally dynamic logic has a clock input which determines whether the device will work in pre-charge or evaluation phase. PMOS is used as the pre-charge transistor and evaluation is done using ...
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How do processor transistor counts keep increasing, without geometric scaling?
Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
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Why is it necessary that the poly line extends the diffusion strip in a layout?
Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
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Setting parameters in SPICE models
I was trying to run some simulations on 45nm technology MOS transistors in Spice. I had a few beginner level questions regarding these models.
If a library says it is for 45nm process node, shouldn't ...
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The unusable state of S-R Latch simulation in LTSpice
I created an S-R Latch in spice using MOS transistors (180nm) and gave noth S and R inputs as 1 (knowing that this state is unusable as both Q and Qbar will be metastable). But I was expecting ...
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Plotting MOS resistances in transmission gates in spice
I am trying to plot the resistance of MOS transistors in transmission gates, as a function of output voltage in ltSpice, as shown in this figure from Jan.M.Rabey:
I have a circuit with same ...
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MOSFET I/V characteristics. How does this mosfet conduct current?
I am currently studying the basics of CMOS design and came across the following problem in Razavi's textbook with respect to a NMOS transistor :
The question is simple:
Let \$V_{SB}\$ = 0 (source-...
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How do the dimensions of a MOS tranistor affect the gain of a CMOS inverter?
I am simulating the voltage transfer characteristic curve of a CMOS inverter, while varying the dimensions of L and W of MOS. Comparing the results for two scenarios, I have the following results:
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Digital isolator capacitor design
I am new to analog design and I need to design a galvanic isolator based upon the edge-based communication** described in digital isolator design guide as a part of a task.
How can I start designing ...
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Is there a modular multiplier design that can give the result in 1 cycle?
I need to perform modular multiplication on two large numbers (more than 10,000 bits wide). I've found papers that give designs that can that calculate the result in N cycles, but in my case, that ...
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Why is an N-type MOSFET used for low-side and a P-type for high-side switching?
Typically an N-MOSFET is used for low-side switching and P-type for high side switching. That's why transmission gates use both an N and a P-type MOSFET.
But I don't understand how a P-type for low-...
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How can I generate a 1 Hz clock from 100 MHz clock using VHDL?
How can I generate a 1 Hz clock from 100 MHz clock using VHDL?
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How does logic 1 get passed through an NMOS pass transistor?
I'm studying pass transistors. One thing I came across in several of the books is that when an NMOS has a logic state HIGH and the input terminal (the schematic below) is also HIGH, the output ...
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Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)
I am unsure which option is best practice from those featured in the title. This is part of some VLSI coursework I am doing in Cadence and so will need to do the layout of this design as well.
For ...
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How to correctly constrain a clock network with lots of mux branches?
Let me simplify a common clock network structure used in my company:
Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs).
Right at the beginning when these sources are &...
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Prevent spikes during transition of inputs in AND gate
Question
Suppose we have a two-input AND gate. The inputs do not change instantly. So, it's not a perfect rectangular signal rather trapezoidal.
Consider the situation when input 1 is transiting to ...
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Question about shortest-path algorithm during synchronous circuit synthesis
In Retiming synchronous circuitry , why put a negative sign to d(u) in step 1 ? Why there is no subtraction operation for W(u, v)...
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What is the current state of the art design rule for SiC VLSI? Technological impediments to making a SiC microcontroller for a Venus lander at 460 °C?
A sub-discussion below Is there any demonstrated or even proposed technology that can sterilize a spacecraft with 100% certainty and yet leave it electronically functional? in Space Exploration SE ...
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Why does lowering VDD increases the delay for digital circuits?
I've preparing for Physical Design Interview and came across couple of explanations that deduce that the delay of logical gates will increase once we reduce VDD. what is the reason?
my intuition sends ...
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What is meant by\$ I_{peak} \$current in CMOS inverter?
This is a snap from Chapter number 5 CMOS inverter, Digital integrated circuit by Jan M Rabaey .
I just wanted to know from where this \$I_{peak}\$ is measured. The direct path current exist till the ...
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