Questions tagged [vlsi]

VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.

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19 views

Why is it necessary that the poly line extends the diffusion strip in a layout?

Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
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23 views

UPF: UPF_SCOPE_NOT_FOUND_ERROR

I am trying to write a upf for the ARM architecture. My test bench and rtl are pretty straight forward. ...
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24 views

virtuoso ERROR (WIA 1175) "Cannot plot waveforms … no waveform data is available"

I am new to Cadence Virtuoso and trying to plot the characteristics of very simple voltage divider. I have included model files from gpdk45 and when I try to simulate, it says: Cannot plot waveform ...
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57 views

Setting parameters in SPICE models

I was trying to run some simulations on 45nm technology MOS transistors in Spice. I had a few beginner level questions regarding these models. If a library says it is for 45nm process node, shouldn't ...
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73 views

The unusable state of S-R Latch simulation in LTSpice

I created an S-R Latch in spice using MOS transistors (180nm) and gave noth S and R inputs as 1 (knowing that this state is unusable as both Q and Qbar will be metastable). But I was expecting ...
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42 views

How is rip up and reroute performed exactly?

I've been teaching myself about VLSI algorithms a bit more and trying to get up to a basic level of knowledge. The basics of maze routing including path finding, multi-destination net routing, multi-...
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32 views

Plotting MOS resistances in transmission gates in spice

I am trying to plot the resistance of MOS transistors in transmission gates, as a function of output voltage in ltSpice, as shown in this figure from Jan.M.Rabey: I have a circuit with same ...
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65 views

MOSFET I/V characteristics. How does this mosfet conduct current?

I am currently studying the basics of CMOS design and came across the following problem in Razavi's textbook with respect to a NMOS transistor : The question is simple: Let \$V_{SB}\$ = 0 (source-...
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47 views

How do the dimensions of a MOS tranistor affect the gain of a CMOS inverter?

I am simulating the voltage transfer characteristic curve of a CMOS inverter, while varying the dimensions of L and W of MOS. Comparing the results for two scenarios, I have the following results: ...
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Digital isolator capacitor design

I am new to analog design and I need to design a galvanic isolator based upon the edge-based communication** described in digital isolator design guide as a part of a task. How can I start designing ...
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51 views

Is there a modular multiplier design that can give the result in 1 cycle?

I need to perform modular multiplication on two large numbers (more than 10,000 bits wide). I've found papers that give designs that can that calculate the result in N cycles, but in my case, that ...
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85 views

Why N type MOSFET is used for low side and P-type for high side switching?

Typically N-MOSFET is used for low side switching and P-Type for high side switching. That's why transmission gates use both N and P-type MOSFET. But I can't correctly understand how a P-Type for the ...
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168 views

How can I generate a 1 Hz clock from 100 MHz clock using VHDL?

How can I generate a 1 Hz clock from 100 MHz clock using VHDL? ...
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Finding Elmore delay if S/D are shared, between two unequal transistors?

If W=3, and Cload = 10, How can we find output pull down delay? If there is no sharing of S/D then the problem is simple C_n=(2+W)C delay = (R/W)(C_n) + (R/W + R/2)(C_load) but when we are sharing S/D ...
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How does logic 1 get passed through an NMOS pass transistor?

I'm studying pass transistors. One thing I came across in several of the books is that when an NMOS has a logic state HIGH and the input terminal (the schematic below) is also HIGH, the output ...
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68 views

Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)

I am unsure which option is best practice from those featured in the title. This is part of some VLSI coursework I am doing in Cadence and so will need to do the layout of this design as well. For ...
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202 views

How to correctly constrain a clock network with lots of mux branches?

Let me simplify a common clock network structure used in my company: Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs). Right at the beginning when these sources are &...
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177 views

Prevent spikes during transition of inputs in AND gate

Question Suppose we have a two-input AND gate. The inputs do not change instantly. So, it's not a perfect rectangular signal rather trapezoidal. Consider the situation when input 1 is transiting to ...
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83 views

Question about shortest-path algorithm during synchronous circuit synthesis

In Retiming synchronous circuitry , why put a negative sign to d(u) in step 1 ? Why there is no subtraction operation for W(u, v)...
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95 views

What is the current state of the art design rule for SiC VLSI? Technological impediments to making a SiC microcontroller for a Venus lander at 460 °C?

A sub-discussion below Is there any demonstrated or even proposed technology that can sterilize a spacecraft with 100% certainty and yet leave it electronically functional? in Space Exploration SE ...
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How do I support 3-D integrated circuit layout design, using OASIS or GDSII?

How do I support 3-D integrated circuit (IC) layout design, using Open Artwork System Interchange Standard (OASIS) or Graphic Data System II (GDSII)? If I add through-silicon vias and or copper-to-...
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1answer
175 views

Why does lowering VDD increases the delay for digital circuits?

I've preparing for Physical Design Interview and came across couple of explanations that deduce that the delay of logical gates will increase once we reduce VDD. what is the reason? my intuition sends ...
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198 views

What is meant by\$ I_{peak} \$current in CMOS inverter?

This is a snap from Chapter number 5 CMOS inverter, Digital integrated circuit by Jan M Rabaey . I just wanted to know from where this \$I_{peak}\$ is measured. The direct path current exist till the ...
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197 views

Propagation and contamination delays with different delays for rising and falling edges

In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way: The propagation delay \$t_{...
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142 views

Ohm's law Vs. Ohm's relation (which one is right)?

Ok, so this might be a stupid question but I just had to ask. We are all taught that Ohm's law is: V = IR I have heard some people that insist that it should be called Ohm's relation instead of ...
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95 views

Which technique is used to create high value resistance inside a IC?

Various ICs have resistances inside them. For example, AVR microcontrollers have an internal 10k pull-up resistor inside them. Which kind of technique is used to design these resistors? If I want to ...
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How to make diodes and bonding pads in Electric (ID design program)?

I'm a beginner user of Electric, a free VLSI/IC design program. Let me preface, that the last time I've used an IC design program was nine years ago at University. We used Cadence Virtuoso back then. ...
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122 views

Capture register value at specific instance in Verilog

I created two always blocks in Verilog. In one always block, one bit register variable is flipping and in other always block, a counter variable is running. Now when counter will reach to a specific ...
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199 views

What is the triangle symbol in circuit diagrams?

What is the triagular symbols shown in the image, is it a buffer or some kind of delay?
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153 views

Why Tcd and Tpd is different in combinational ckt?

In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons: Different rising and falling delays, ...
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57 views

what does qualcomm MDM6085 do?

This is my first question in this stack exchange. I found my old Reliance Netconnect+ modem and decided to open it up. There is a micro chip with the name QUALCOMM MDM6085 on the top left and EAB857.0 ...
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312 views

Calculating propagation delay for a logic circuit

Given the above combinational logic diagram, How to calculate the propagation delay? AND->OR->AND-NOT NOT->AND->NOT I see the above two longest paths. So what I understand is just take ...
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370 views

Which software is used to design (and simulate) IC?

Currently I'm using Proteus to design and simulate all of my schematics. Is there any (free) software for designing and simulating ICs? I searched the Internet and found Cadence and Glade Thanks!
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118 views

Why can't conductors be used in making ICs (integrated circuits) instead of semiconductors? [closed]

I really wanted to ask why we can not control flow of electrons in conductors. Can I not say if a current is flowing in a conductor it is 1 and when I disconnect the supply it is 0. Can you elaborate ...
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36 views

IV characteristics of NMOS transitor

I have used the model of the GPDK90 transitor in Cadence. I have few questions regarding the IV characteristics: Why does the threshold voltage change with change with Vds (Vds= 0, 1.25, 2.5, 3.75 ...
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165 views

How do ASIC designers approach designing for extremely low supply voltages like 0.3V?

In ASIC design, there is a tradeoff between performance and energy efficiency. Since most consumer CPU's are designed for maximum performance, they operate at high voltages and clock frequencies, ...
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384 views

Why does Moore Finite State Machine need more states than Mealy Finite State Machine?

I was reading about finite state machines. I read about Moore and Mealy machine and also the state representation. I read that in the Moore machine the output depends on the present state only and in ...
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1answer
61 views

How to find what circuitry is required for synthesis of following digital VLSI design problem?

My thoughts: Here price of chocolate is increasing in Geometric progression with common ratio 2 and first term 1, so on nth day price of chocolate will be $T_{n}=2^{n-1}$\ irrespective of wheather ...
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81 views

Systemverilog interface definition - lint error message

I'm using Systemverilog interfaces to enable the implementation of generic functions. The interface is defined in one file as follows: ...
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20 views

Path exceptions modeling for ETM

On page 3 of Hierarchical Timing Analysis: Pros, Cons,and a New Approach , how is set_output_delay related to set_multicycle_path here in this case ? and how to re-code the path exceptions ? Any ...
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756 views

Why does decreasing the CMOS supply voltage also decrease the maximum circuit frequency?

In CMOS circuit design, we know dynamic power is proportional to \$V_{dd}^2Cf\$, so the best way to reduce dynamic power is to reduce \$V_{dd}\$. However, according to the textbook, Keeping the same ...
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93 views

Needed help in drawing CMOS design and euler path p-tree ,n-tree for boolean function

I have the expression \$Z=(A(D+E)+(BC))'\$, I'm trying to draw CMOS logic but I guess I've gone wrong somewhere. I'm unable to draw Euler path for this diagram
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?

I've been studying to understand Static Timing Analysis aka STA. One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
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156 views

what is the specific reason for using FIFO in asynchronous domain at VLSI?

I was wondering that the reason of using FIFO in asynchronous domain at VLSI. Basically, to prevent x propagation in asynchronous domain(aka CDC domain), I was taken care of 2 stage F/F method for ...
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505 views

Why do we declare the inputs of our design as reg in testbench and outputs as wire?

Why do we declare the inputs of our design as reg in testbench and outputs as wire?
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91 views

Load Capacitance in CMOS Circuits

I am studying VLSI Coursers and I came up to a question. what happens if we don't use output load in CMOS circuits? what happens to overshoot/undershoot and circuit delay? thanks
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54 views

General CMOS circuit

In any CMOS circuit like an inverter or an n-input NOR or NAND gate, where the pMOS network is connected at the top to Vdd source terminal and nMOS network is connected at the bottom to the ground ...
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263 views

What is the origin of the "iso [frequency/voltage/power]" terminology?

In the VLSI and computer architecture world, it is common to hear terms like "iso frequency" or "iso power" when comparing the performance of different designs. My understanding is ...
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275 views

Errors in VHDL code

The VHDL code was written by me for a 4-bit PIPO DFF register. I have been encountering some errors when i did so. Kindly check the code and errors below. ...
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Why would an AND gate need six transistors?

I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense ...

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