PIC16F18855 adc read mismatch

Question

I wrote a code for pic16f18855 analog voltage to digital value reading. but I noticed that analog voltage connected to pin RA0 read with RA1 and analog voltage connected to pin RA1 read with RA2 and analog voltage connected to pin RA2 read with RA0. what is the problem. i am trying for three days but didnot get any clue. this is a simple code but i didnt understand what is the problem. please have a look on the following code.

#pragma config FEXTOSC = HS // External Oscillator mode selection bits (HS (crystal oscillator) above 4MHz; PFM set to high power)
#pragma config RSTOSC = EXT1X // Power-up default value for COSC bits (EXTOSC operating per FEXTOSC bits)
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled; i/o or oscillator function on OSC2)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit (FSCM timer enabled)

// CONFIG2
#pragma config MCLRE = ON // Master Clear Enable bit (MCLR pin is Master Clear function)
#pragma config PWRTE = ON // Power-up Timer Enable bit (PWRT enabled)
#pragma config LPBOREN = OFF // Low-Power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = OFF // Brown-out reset enable bits (Brown-out Reset Disabled, SBOREN bit is ignored)
#pragma config BORV = LO // Brown-out Reset Voltage Selection (Brown-out Reset Voltage (VBOR) set to 1.9V on LF, and 2.45V on F Devices)
#pragma config ZCD = OFF // Zero-cross detect disable (Zero-cross detect circuit is disabled at POR.)
#pragma config PPS1WAY = ON // Peripheral Pin Select one-way control (The PPSLOCK bit can be cleared and set only once in software)
#pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will cause a reset)

// CONFIG3
#pragma config WDTCPS = WDTCPS_0// WDT Period Select bits (1:1)
#pragma config WDTE = OFF // WDT operating mode (WDT enabled regardless of sleep; SWDTEN ignored)
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)

// CONFIG4
#pragma config WRT = ON // UserNVM self-write protection bits (Write protection on)
#pragma config SCANE = available// Scanner Enable bit (Scanner module is available for use)
#pragma config LVP = OFF // Low Voltage Programming Enable bit (High Voltage on MCLR/Vpp must be used for programming)

// CONFIG5
#pragma config CP = ON // UserNVM Program memory code protection bit (Program Memory code protection enabled)
#pragma config CPD = ON // DataNVM code protection bit (Data EEPROM code protection enabled)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
#define _XTAL_FREQ 20000000

#include <xc.h>
#include <pic.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <stdint.h>



uint8_t adc(uint8_t ch)
{
    ADPCH = ch;
    
    // Start the conversion
    ADCON0bits.ADGO = 1;
    
    // Wait for the conversion to complete
    while (ADCON0bits.ADGO);
    
    __delay_us(20);  // Introduce a short delay for settling
    
    return ADRESH;
}


int main()
{
    
  TRISC=0x00;  
    
  LATA  = 0xFF;
  TRISA  = 0xFF;
  ANSELA = 0x3F;
  ADCLK = 0x0F;
  // ADGO stop; ADFM left; ADON enabled; ADCONT disabled; ADCS FOSC/ADCLK;
  ADCON0 = 0x80; 
  

while(1)
{

     
      if( adc(0)>127)
        {
        PORTCbits.RC3=1;
        }
        else
        {
        PORTCbits.RC3=0;
        }
       __delay_ms(100);  
     
     
     
     
   
      if( adc(1)>127)
        {
        PORTCbits.RC4=1;
        }
        else
        {
        PORTCbits.RC4=0;
        }  
   
        __delay_ms(100); 
     
     
      if( adc(2)>127)
        {
        PORTCbits.RC5=1;
        }
        else
        {
        PORTCbits.RC5=0;
        }   
       __delay_ms(100); 
  
  
 
  

}
}```

Answer 1

Microchip cautions users that selecting a new ADC channel, then immediately starting an ADC-acquire-sample can lead to unexpected results similar to what OP has encountered.
The reason given involves the ADC's internal sampling capacitor - time is required for it to charge and settle to a new analog voltage. It is suggested to add a small delay after a new channel is selected but before ADC's ADGO bit is raised (which starts a new ADC sample acquire). The delay is not needed if one ADC channel is always selected.

OP's code attempts to add a 20 microsecond delay, but placed in the wrong spot: after launching a new ADC-acquire. Setting ADGO disconnects the sampling capacitor from the selected channel, which has too-recently been changed.

delay for charging/discharging is needed after channel select, and before ADCCON0bits.ADGO bit is set. Once ADCCON0bits.ADGO is internally reset (indicating completion of the new acquire), a new ADC result ADRESH, ADRESL are immediately valid...

uint8_t adc(uint8_t ch)
{
    ADPCH = ch;
    __delay_us(20);  // A short delay for settling    
    // Start the conversion
    ADCON0bits.ADGO = 1;
    
    // Wait for the conversion to complete
    while (ADCON0bits.ADGO);
    
    return ADRESH;
}