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I am designing a current mode flyback, and am using the UCC28C51 IC from Texas Instruments. I don't intend on using the error amplifier built into the chip, I intend on having the optocoupler transistor output drive the COMP pin of the IC directly. The E/A output is current limited to allow this configuration when you ground the FB pin. How would I model that current limited 5V output so I can put it in my loop gain analysis LTSpice sim as the "pullup" resistor for my opto output?

UCC28C51 Functional Block Diagram

Example showing bypassing of E/A

The two images above show the functional block diagram of the UCC28C51 and an example application diagram showing a configuration that bypasses the E/A.

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    \$\begingroup\$ Hello Michael, you can have a look at the two answers I gave on SE and here. The op-amp, once disabled, no longer plays a role (besides the bias point adjustment with its 1-mA CC source) and you can model the opto loaded by the pull-up resistance driving the divide-by-3 internal network, later clamped at 1 V when reacing the CS comparator. \$\endgroup\$
    – Verbal Kint
    Commented Jun 7 at 11:55
  • \$\begingroup\$ So once disabled by grounding the FB pin and adding the COMP pin pullup to VREF, the opto gain equations referencing Rpullup in your books is still just that resistance value added between VREF and the COMP pin? \$\endgroup\$
    – Michael Beckwith
    Commented Jun 7 at 14:21
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    \$\begingroup\$ The thing that I ignore are the values of the 2R/R resistances loading in the CMP-to-CS path which will change the Thévenin resistance at the CMP pin but we can neglect their effect and, in this case, yes, the pull-up resistance is alone for the small-signal equations. \$\endgroup\$
    – Verbal Kint
    Commented Jun 7 at 16:41

2 Answers 2

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As @Verbal Kint commented, that 1mA from the E/A simply shifts the bias points slightly and doesn't play a role in the AC analysis I am doing. So while my question of how to model that limited source current from the E/A isn't answered, ultimately I don't need to do it.

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Simulating it, short of having a representative model for the chip, might not be very feasible. The datasheet does not describe the V(I) characteristic of the CMP pin, for example.

Error amp source current is rated 1mA typical, with no maximum listed. While it might not be much higher than this in the worst case, a guarantee would be preferable, so we can properly design a pull-down (overdrive) circuit.

I would suggest an alternative arrangement, then.

The easiest way to guarantee performance, is to wire it as an inverting unity gain amplifier: use e.g. 10k resistors, from input, to FB, to CMP. The opto pulls down on the input (FB is biased to 2.5V so the input can always be pulled towards GND), directly or with additional pull-up resistor to increase bias current (perhaps to improve bandwidth).

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