Can any SPI device be daisy chained?

Question

I have an application where I need to read from a 2 m long chain of 20 or so IMUs. Space is a concern, so I would ideally find a way to put them all on a single bus in a way that minimizes wire count. I think SPI daisy chaining could be a good method, but I have minimal experience in this area. Can any SPI device be daisy chained, or does the datasheet have to explicitly mention support for daisy chaining?

SPI daisy chaining is my top approach as it minimizes ICs and wire count, but I am also considering shift registering by adding a microcontroller next to each IMU, I2C with address translators next to each IMU, SPI with demultiplexer for to minimize chip select lines, and I3C.

Answer 1

Can any SPI device be daisy chained?

No.

Generally it would mean that a chip would clock out bits sent to it. Not all chips will do that. Even if some or all chips did do that, they would send out something, so the first chip would get correct data in, but also the first chip and the rest of them would send incorrect data out to next chips.

It will only work with certain chips, such as shift registers that only pass out data clocked into them and don't care what is clocked in until the data is latched in.

Any register based chip like an IMU will assume first it is sent a register address to access, and if that access is read or write. So they can't be chained.

Answer 2

Devices which lack a serial output pin would be an obvious exception. There are some such devices, can't remember which supplier but it was Linear Technology or Analog Devices (now the same company) or Burr-brown (now TI). Probably a DAC or similar. Some devices need different SPI modes (there are 4 possible modes) and probably some don't behave nicely when you give them "unnecessary" clock pulses.

If all your devices have an output pin that is tristated when /CS is de-asserted you can run them in parallel and just strobe the /CS pin for the active SPI target chip, re-configuring the SPI mode and clock rate between accesses. That allows you to use on-chip SPI hardware and share it between devices. If you have a huge number of similar chips then daisy-chaining might make more sense.