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The Ettus Research Software Defined Radio B210 has a range of 70 MHz - 6 GHz, a Bandwidth of 56 MHz and its maximum ADC rate is 61.44 MS/s. Doesn't Nyquist theorem state that the sampling rate should be 2*Fmax, where Fmax here is 6 GHz ?

EDIT: the board uses Analog Devices AD9361 RFIC

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    \$\begingroup\$ The key is that the goal of sampling isn't to preserve a detailed time-domain picture of the radio signal. That is not necessary because the actual content which is carried in the signal doesn't rely on the amplitude details of every individual oscillation cycle of the carrier. \$\endgroup\$ – Kaz Nov 17 '13 at 21:39
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Pease note the following:

  1. The device actually does not sample RF. It downconverts to 0 Hz (on frequency downconversion) and then samples it.

Internally it has various analog stages to control gain, bandwidth, as well as state machines to overcome limitations of direct conversion.

For details please check the following block diagram of the AD9361. https://github.com/analogdevicesinc/iio-oscilloscope/blob/master/block_diagrams/AD9361.svg

  1. The RF bandwidth can be 56 MHz and 64 MSPS will be sufficient. Why? Because the device is outputting 12 bits of I & 12 bits of Q samples at each MSPS rate specified. Therefore real sampling rate can be assumed to be 2X of specified MSPS.
  2. The device samples RF at much higher rate but the real reason for that is a little different than just satisfying NYQUIST.
    • the type of ADC inside the device requires higher sampling to generate desired 12 bit resolution. It is an advanced Sigma-delta-modulator (3 bit SDM + sign i.e. -4 to 4). With some math, it converts these 3 bit values and generates 12 bit value. For details please check the AD9361 Reference manual section related to ADC overload detector.
    • Device needs to do some filtering so aliasing doesn't happen. In order to do that, it samples at much higher rate, then digitally downsamples. During this process, it attenuates ADC images.There is also an additional FIR filter inside for correcting downconversion imperfections.
    • Note that the device still needs external filters for good performance.
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Have a look at the updated block diagram of the chip on the B200.

https://github.com/analogdevicesinc/iio-oscilloscope/blob/master/block_diagrams/AD9361.svg

A couple things:

  • the max ADC rate is not 61.44, it's actually 640MSPS, but that assumes some decimation along the way.
  • the max data output is 61.44 MSPS
  • the max RF bandwidth is 56 MHz, and is set by the analog filters, not the ADC sample rate.

Many more questions can be answered on ADI's web site: https://ez.analog.com/community/wide-band-rf-transceivers

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Sampling results in duplicating the input signal in the frequency domain. The Nyquist criterion specifies how you have to sample a signal from DC up to Fmax without aliasing. However, with the proper ADC, you can sample a signal from F1 to F2 where both F1 and F2 are higher than your sample rate. All you need to do is make sure that there won't be any signals below F1 or above F2 that will be aliased with the signal you want. This requires a bandpass filter instead of a low pass filter. The sample rate only determines the receive bandwidth, not the receive frequency range. This is called undersampling, and it is very common in radio receivers because it can eliminate one or more mixers and local oscillators.

Wikipedia: http://en.wikipedia.org/wiki/Undersampling

In this case, it's also possible that they are using a mixer and LO to downconvert the input signal to a lower frequency for reception. Their block diagram is rather lacking.

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  • \$\begingroup\$ If I use the equations in your link, then n=Fh/(Fh-Fl) = 6000/(6000-70)=1.01, and since we need integers, then n=1. Therefore downcoverting is not going to "work" or "give any advantage", since you still need sampling rate>= 2* Fh / 1 = 2*Fh = 1200 MS/s. \$\endgroup\$ – student1 Nov 17 '13 at 21:12
  • \$\begingroup\$ OK I think we need to consider the BW to be 56MHz not (6000-70) MHz, but still, the Sampling rate should be 2*56 = 112MS/s, larger than the 61.44 MS/s ?? \$\endgroup\$ – student1 Nov 17 '13 at 21:23
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    \$\begingroup\$ "Bandwidth of 56 MHz and its maximum ADC rate is 61.44 MS/s" suggests a dual-channel IQ system where the bandwidth ranges from -FS/2 to +FS/2. Having the second channel in quadrature permits positive and negative frequencies to be distinguished from each other - if either of the quadrature components is removed, then looking only at the remaining one they alias indistinguishably about 0. \$\endgroup\$ – Chris Stratton Nov 17 '13 at 21:29
  • \$\begingroup\$ @ChrisStratton This makes sense, I have checked the datasheet and this is indeed the case. \$\endgroup\$ – student1 Nov 17 '13 at 22:10
  • \$\begingroup\$ Yeah, I think that's probably what's going on here instead - downconverting and using an IQ mixer and sampling the output of that with the ADC. Now, it could still be undersampling the output of the IQ mixer depending on how it's designed. \$\endgroup\$ – alex.forencich Nov 17 '13 at 22:10

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