# Visualising data rate as square waves (Converting bits per second into hertz) for selecting ADC sampling frequency

I know that bits per second and hertz are two different units. This question will help me in designing an oscilloscope with proper ADC sampling frequency for viewing communication protocols.

Just imagine a communication protocol(eg: I2C) which has a data rate of 1Mbps. As per the protocol, there are different fields where we can keep data, address etc. But I am currently assuming that each bits in this protocol is toggling one after the other. Then this looks like a square wave.

In a square wave, the fist half will high(Logic 1) and the second half will be low(Logic 0) or vice versa. So in one cycle we have two bits. As per this visualisation 1Hz i.e 1 cycle/sec is equivalent to 2bits/sec(or 2bps).

Similarly for 1Mbps data rate, there will be 1000000 bits per second. If we assume each bit is inverse of the other(i.e they toggle like a square wave) and as per our calculation, 2bits will be present in one cycle of square wave, then 1000000 bits per second = 500000Hz (1000000bps /2 bits in one cycle). So 1Mbps is equivalent to 500kHz square wave.

Is my visualisation correct(I converted bits per second to hertz)?

I want to make a USB oscilloscope in which I want to select a proper sampling frequency for the ADC. So in this case if I assume 1Mbps as 500kHz, then for a good signal display(signal reconstruction based on the ADC samples), sampling should be done at 10 times the signal frequency i.e 5Mega samples per second (500kHz *10 = 5MHz)

Is this calculation correct ?

Also does this mean that I can view this communication protocol's voltage levels clearly on a oscilloscope having bandwidth of 5MHz (500kHz *10)?

EDIT: For serial communications the pulse width, in time, for each bit is a very important parameter. If your data rate is 1Mbps then you expect the pulse width to be 1$\mu$s, but if you only sample that signal at 5MHz then your pulse width measurements will be $\pm$0.1$\mu$s which is pretty rough. More important in my mind are setup and hold measurements. You want to know how long the data signal is stable before a clock edge and how long it remains valid after a clock edge. Specifications for setup and hold may be tens of nanoseconds for a 1Mbps data rate, and it will be very difficult to observe these when sampling every 200ns.
For debugging serial communications the instrument you really want is a logic analyzer. These devices can sample data at very high frequencies but they don't try to measure the actual voltage of the signal, only whether it is a valid logic 1 or 0. They also have other capabilities that are made possible by treating the inputs as digital data rather than analog voltages.