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I am new to electronics, I'm trying to get my head around this concept.

As I understand it, on any processor, you will be able to switch an output on or off, at a rate no faster than the speed of that processor. So a 8Mhz chip could (ideally) switch an input on or off at a rate of 8 million times a second.

HDMI 2.0 specification calls for a transmission rate of up to 18 Gbit/s. How is this possible without an 18Gzh processor?

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  • \$\begingroup\$ HDMI uses three connections in parallel to transfer that data. Therefore, the maximum data-rate per wire (differential pair, actually) is 6 Gbit/s. \$\endgroup\$ Commented Jan 24, 2014 at 9:38

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Such fast outputs are never handled directly by a processor. That would be called "bit banging" and is really only practical for bit rates that are a small fraction of the CPU instruction cycle rate (note that a chip with an 8MHz external clock might internally run at 2MHz or 200MHz instruction rate).

Instead there are peripherals that are dedicated arrangements of gates, flip-flops and registers that are used to serialize data, perhaps directly from memory (DMA = direct memory access). There may be an internal memory bus dedicated just to getting data out of a frame buffer at that rate. In the case of HDMI there would likely be a dedicated graphic processor (GPU) optimized for video processing.

In the case of the Broadcom BCM2835 SOC used in the Raspberry PI, the GPU is a VideoCore 4 ARM1176. It would be nice to see the internals of such a chip, but Broadcom holds the cards close to the chest, and an NDA and a substantiated intent to use a substantial volume of chips is the price of entry.

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  • \$\begingroup\$ Ok, using DMA, would the theatrical maximum transfer rate be the instruction frequency times the largest register in bits (say 32)? It looks like DMA is mostly connected to a level1 or level2 cache and not to the registers directly, so maybe the maximum rate would really be the register size times the level 1 cache speed. If this is the case, even the raspberry Pi at 700mhz should be able to pull off 16gb/s. So the short answer is, "by transmitting in parallel". \$\endgroup\$
    – Beachhouse
    Commented Jan 24, 2014 at 15:29
  • \$\begingroup\$ This still doesn't quite answer my question though. I think now I have a better idea what I'm trying to say. "In order to transmit at given rate, is it fair to say there are transistors switching at that rate?" So with the 6Gb/s HDMI rate (thanks Connor wolf), there are transistors that are switching at 6 billion times a second. And using gates it re-parallels the signal and there by slowing it down to a processor manageable rate. Is that correct? \$\endgroup\$
    – Beachhouse
    Commented Jan 24, 2014 at 15:38

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