Skip to main content
2 of 2
deleted 64 characters in body
nidhin
  • 8.4k
  • 3
  • 31
  • 47

Is inverting the output of a CMOS network a bad practice?

I am an Electronics & Comm. Engg. 3rd yr. student and we are learning CMOS logic for the first time this semester under the subject VLSI design.
While designing for the logic equation: \$Y= A + B.C\$, the professor first wrote it as \$\overline{\overline{A+B.C}}\$ , then simplified it by De Morgan's laws and then implemented it with CMOS.

I was wondering if it would be better to implement \$\overline{A+B.C}\$ and then use a CMOS inverter to invert to output since this would need lesser number of gates. When I asked the professor if it can be done that way, he said there won't be any sense in using CMOS if used that way. I didn't understand what this means, and why it cannot be implemented this way.

P.S. I'm new on Stack Exchange. Apologies for any mistakes in my way of putting the question.