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I am an Electronics & Comm. Engg. 3rd yr. student and we are learning CMOS logic for the first time this semester under the subject VLSI design.
While designing for the logic equation: \$Y= A + B.C\$, the professor first wrote it as \$\overline{\overline{A+B.C}}\$ , then simplified it by De Morgan's laws and then implemented it with CMOS.

I was wondering if it would be better to implement \$\overline{A+B.C}\$ and then use a CMOS inverter to invert to output since this would need lesser number of gates. When I asked the professor if it can be done that way, he said there won't be any sense in using CMOS if used that way. I didn't understand what this means, and why it cannot be implemented this way.

P.S. I'm new on Stack Exchange. Apologies for any mistakes in my way of putting the question.

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When implemented in CMOS, simple inverting logic gates take one stage, that includes inverter, NAND, NOR.

Non-inverting logic gates take two stages. For example, a buffer would actually be two inverters back to back. An AND gate would actually be a NAND gate plus an inverter...

I assume your professor did the following:
\$Y = A + B * C = \overline{\overline{A} * (\overline{B * C})}\$
So the actual logic required are one inverter (for A), one NAND (for B,C), one NAND (final output).

If implemented as you suggested, it would actually be like:
\$Y = A + B * C = \overline{(\overline{A + \overline{(\overline{B * C})}})}\$
So it would be an inverter+NAND (for B,C), an inverter+NOR (final output).

So it takes one extra inverter -- not so bad in this case. But there is a big speed disadvantage, 4 levels vs 2.

This quote "he said there won't be any sense in using CMOS if used that way" may have lost something in translation. But I am guessing that your professor was trying to convey the fact that inverting logic gates are the natural building blocks of CMOS logic and are in general more efficient than the non-inverting counterparts.

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  • \$\begingroup\$ Actually he further made the /$/overline{B*C}/ into NOR so it was 3 inverters, 1 NOR and 1 NAND. Anyway, thanks. I suppose that's what he meant, as @akellyirl says, inverting gates give lower area and delay. \$\endgroup\$ – Abhinav Mar 15 '15 at 8:37
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Standard CMOS gates used in IC design are inverting for a variety of reasons, including lower area and delay compared to the non inverting versions. See this Question. This also needs to be taken into account; not just the number of gates.

It would be inefficient to use an inverter when the inversion can be optimised away in the logic by using an inverting logic function such as NAND, NOR etc. (Inverting logic being preferred).

Sometimes a noninverting function is required, in which case it's just as easy to implement it with a final inverter. In IC design this is even the preferred way of doing it because inverters come in a wide range of drive strengths, so the final inverter in the logic can drive a long path to the next area of logic if necessary, and is smaller than the equivalent strength buffer (non-inverting).

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  • \$\begingroup\$ Thanks. Makes it clearer. However, I'm still a little confused as you said sometimes this is the preferred way in IC design. So overall what is a better practice, to invert final output or simplify by De Morgan's and give inverted inputs? \$\endgroup\$ – Abhinav Mar 14 '15 at 12:57
  • \$\begingroup\$ @Abhinav - please read the rest of the sentence, where he explains why it may be preferred. The part that starts "because inverters". \$\endgroup\$ – WhatRoughBeast Mar 14 '15 at 13:50
  • \$\begingroup\$ @WhatRoughBeast Yes actually I did not understand that part only. :P \$\endgroup\$ – Abhinav Mar 14 '15 at 17:22
  • \$\begingroup\$ @Abhinav Ah. When designing an IC, you have to make a tradeoff. In order to maintain a given speed, you need to charge a capacitance which depends on how many gates are driven and how far away they are. In general, the larger the output transistor area, the more current it will provide (how strong it is). But at the same time, you obviously want to keep the total chip area as small as possible, so you don't make gate output drivers any stronger than necessary. Does this help? \$\endgroup\$ – WhatRoughBeast Mar 14 '15 at 20:49
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Well, one of the tricks used in CMOS design to simplify logic is to selectively invert entire signals. The overall logic function remains the same, but it is possible to simplify the stages and remove extra inverters. Sometimes it requires adding a couple of inverters to the inputs and outputs, but in general this technique can significantly simplify the implementation. This decreases area, power consumption, and propagation delay. This is a common technique used when building large adder trees in things like multipliers. The layers in the tree are built alternately with adders with inverted outputs and adders with inverted inputs. This results in a very significant savings in area, power, and propagation delay by removing a very large number of inverters. I believe the synthesis tools will perform this sort of optimization automatically.

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