I am doing an allgorithmic state machine in VHDL. It models a slot machine. It uses debouncing for the start and end input signals. I need to implement it later on a Basys 3 FPGA. The start and end input signals are modeled with the FPGA buttons. The frequency of the CLK signal of the Basys3 FPGA is 100 MHz. Therefore the period of CLK must be 10^-8 seconds= 10*10^-9 seconds = 10 ns.

• What time length do you recommend for the press debouncing time when pressing the buttons of the Basys3?
• What time length do you recommend for the release debouncing time when releasing the buttons of the Basys3?