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Results tagged with simulation
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user 459627
About tools to simulate circuits. Specify the tool used.
1
vote
1
answer
29
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Verilog - problem reading giving wrong value at interconnected bus
I have the task of designing an 8x8 bit memory in Verilog using CMOS. (orginally asked at Verilog - 8x8 memory unit - wrong value read, but asked to provide more details).
Currently, I have the follow …
- 35
0
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Memory module with SR-Latch - value overritten when writing to another cell
The problem appeared to be caused by some problems with the SR latch.
After adding a little delay on one of the NOR-gates, it seems to work perfectly.
Fix is the #1 in:
nor #1 latch_upper(Q, Q_not, R) …
- 35
1
vote
2
answers
46
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Memory module with SR-Latch - value overritten when writing to another cell
== expected_outp) begin
$display("Read cell 1 FAILED: Expected %h, Got %h", expected_outp, outp);
end else begin
$display("Read cell 1 PASSED: Data %h", outp);
end
// End simulation …
- 35
1
vote
1
answer
15
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Verilog - 8x8 memory unit - wrong value read
I have the task of designing a 8x8 bit memory in Verilog using CMOS.
Currently, I have the following:
Bitcell - takes in signals sel (if its selected), rw (read = 0, write = 1) and input.
If sel=0, o …
- 35