In my digital electronics project I need to calculate dot product of two vectors a and b (256 length of each). Following the basic concept, I need to calculate \$ \sum_{k=1}^{256} a_kb_k \$. Each element of vectors is 4-bit binary number. This doesn't seems to a difficult task in verilog where I can implement this as in XILINX ISE.

sum=0;

for(i=1,i<257,i=i+1)

sum=sum+ \$a_ib_i \$

Furthur I need to implement this on FPGA. But here I got confused in two concept:

1. Do I need to write the module for 'full adder' and added the inputs previous sum and \$a_i b_i\$ bit by bit and store output in sum. Or simply xilinx will automatically implement the full adder during synthsize.

2. Is it valid to use for loop insted of writing always@(condition) beacause on FPGA we have clock as a control signal. Or in this case also xilinx itself will implement/control the for loop by clock signal.

In my digital electronics project I need to calculate dot product of two vectors a and b (256 length of each). Following the basic concept, I need to calculate \$ \sum_{k=1}^{256} a_kb_k \$. Each element of vectors is 4-bit binary number. This doesn't seems to a difficult task in verilog where I can implement this as in XILINX ISE.

sum=0;

for(i=0,i<256,i=i+1)

sum=sum+ \$a_ib_i \$

Furthur I need to implement this on FPGA. But here I got confused in two concept:

1. Do I need to write the module for 'full adder' and added the inputs previous sum and \$a_i b_i\$ bit by bit and store output in sum. Or simply xilinx will automatically implement the full adder during synthsize.

2. Is it valid to use for loop insted of writing always@(condition) beacause on FPGA we have clock as a control signal. Or in this case also xilinx itself will implement/control the for loop by clock signal.

In my digital electronics project I need to calculate dot product of two vectors a and b (256 length of each). Following the basic concept, I need to calculate \$ \sum_{k=1}^{256} a_kb_k \$. Each element of vectors is 4-bit binary number. This doesn't seems to a difficult task in verilog where I can implement this as in XILINX.

sum=0;

for(i=1,i<257,i=i+1)

sum=sum+ \$a_ib_i \$

Furthur I need to implement this on FPGA. But here I got confused in two concept:

1. Do I need to write the module for 'full adder' and added the inputs previous sum and \$a_i b_i\$ bit by bit and store output in sum. Or simply xilinx will automatically implement the full adder during synthsize.

2. Is it valid to use for loop insted of writing always@(condition) beacause on FPGA we have clock as a control signal. Or in this case also xilinx itself will implement/control the for loop by clock signal.

In my digital electronics project I need to calculate dot product of two vectors a and b (256 length of each). Following the basic concept, I need to calculate \$ \sum_{k=1}^{256} a_kb_k \$. Each element of vectors is 4-bit binary number. This doesn't seems to a difficult task in verilog where I can implement this as in XILINX ISE.

sum=0;

for(i=1,i<257,i=i+1)

sum=sum+ \$a_ib_i \$

Furthur I need to implement this on FPGA. But here I got confused in two concept:

1. Do I need to write the module for 'full adder' and added the inputs previous sum and \$a_i b_i\$ bit by bit and store output in sum. Or simply xilinx will automatically implement the full adder during synthsize.

2. Is it valid to use for loop insted of writing always@(condition) beacause on FPGA we have clock as a control signal. Or in this case also xilinx itself will implement/control the for loop by clock signal.